Publications

  1. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    W. Perez, J. Velasco-Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    Proceedings of the 2008 14th IEEE International On-Line Testing Symposium

  2. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    NASA/ESA Conference on Adaptive Hardware and Systems, 2008. AHS '08
    DOI: 10.1109/AHS.2008.59

  3. A graph-based representation of Gene Expression profiles in DNA microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    Proceedings of IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB) 2008
    DOI: 10.1109/CIBCB.2008.4675762
    KEYWORDS: genetic expression; gene expression; diseases; data structures; data models; dna; classification algorithms; chemical technology; artificial neural networks; bioinformatics
    ABSTRACT: This paper proposes a new and very flexible data model, called gene expression graph (GEG), for genes expression analysis and classification. Three features differentiate GEGs from other available microarray data representation structures: (i) the memory occupation of a GEG is independent of the number of samples used to built it; (ii) a GEG more clearly expresses relationships among expressed and non expressed genes in both healthy and diseased tissues experiments; (iii) GEGs allow to easily implement very efficient classifiers. The paper also presents a simple classifier for sample-based classification to show the flexibility and user-friendliness of the proposed data structure

  4. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008
    DOI: 10.1109/ISIE.2008.4677077

  5. A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices
    L. Sterpone, N. Battezzati, M. Violante
    DOI: 10.1145/1366224.1366228
    ABSTRACT: Reconfigurable logic devices such as SRAM-based Field Programmable Gate Arrays (FPGAs) are nowadays increasingly popular thanks to their capability of implementing complex circuits with very short development time and for their high versatility in implementing different kind of applications, ranging from signal processing to the networking. The usage of reconfigurable devices in safety critical fields such as space or avionics require the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), in order to protect their functionality against radiation effects. While these techniques allow to increase the protection capability against radiation effects, they introduce several penalties to the design particularly in terms of performances. In this paper, we present an innovative placement algorithm able to implement fault tolerant circuits on SRAM-based FPGAs while reducing the performance penalties. This algorithm is based on a model-based topology heuristic that address the arithmetic modules implemented on the FPGA reducing the interconnection delays between their resources. Experimental evaluations performed by means of timing analysis and fault injection on two industrial-like case studies demonstrated that the proposed algorithm is able to improve the running frequency up to the 44% versus standard TMR-based techniques while maintaining complete fault tolerance capabilities

  6. A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
    K. Christou, M. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    26th IEEE VLSI Test Symposium
    DOI: 10.1109/VTS.2008.37

  7. A novel methodology for diversity preservation in evolutionary algorithms
    G. Squillero, A. Tonda
    roceedings of the 2008 GECCO conference companion on Genetic and evolutionary computation
    DOI: 10.1145/1388969.1389049

  8. AN EFFICIENT METHODOLOGY FOR REDUCING SoC TEST DATA VOLUME ON LOW-COST TESTERS
    P. , M. Sonza Reorda

  9. An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices
    P. Bernardi, F. Gandino, F. Lamberti, B. Montrucchio, M. Rebaudengo, E. Sanchez
    Proc. 4th European Conference on Circuits and Systems for Communications

  10. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda

  11. An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    Lecture Notes in Computer Science (vol 4974)
    DOI: 10.1007/978-3-540-78761-7_22
    ABSTRACT: Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmark

  12. An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso
    13th IEEE European Test Symposium, 2008
    DOI: 10.1109/ETS.2008.27

  13. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
    P. Bernardi, M. Sonza Reorda
    DOI: 10.1109/DATE.2008.4484685

  14. Coping with Obsolescence of Processor Cores in Critical Applications
    F. Abate, M. Violante

  15. Differential gene expression graphs: A data structure for classification in DNA microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    Proceedings of IEEE 8th International Conference on BioInformatics and BioEngineering (BIBE) 2008
    DOI: 10.1109/BIBE.2008.4696689
    KEYWORDS: bioinformatics; classification tree analysis; dna; data analysis; data structures; decision trees; feature extraction; gene expression
    ABSTRACT: This paper proposes an innovative data structure to be used as a backbone in designing microarray phenotype sample classifiers. The data structure is based on graphs and it is built from a differential analysis of the expression levels of healthy and diseased tissue samples in a microarray dataset. The proposed data structure is built in such a way that, by construction, it shows a number of properties that are perfectly suited to address several problems like feature extraction, clustering, and classification

  16. Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips
    F. Abate, L. Sterpone, M. Violante

  17. Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors
    P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 4974)
    DOI: 10.1007/978-3-540-78761-7_23
    ABSTRACT: This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and exploits both gate- and RT-level descriptions of the processor: the former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is used for the automatic generation of test programs able to excite and propagate fault effects, based on a fast RTL simulation. Experiments on an 8-bit microcontroller show that the proposed method is able to generate suitable test programs more efficiently compared to existing approaches

  18. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/MTV.2007.14

  19. On the Static Cross Section of SRAM-Based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DOI: 10.1109/REDW.2008.24

  20. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    L. Sterpone, M. Aguirre, J. Tombs, H. Guzman
    IEEE Design, Automation and Test in Europe

  21. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, M. Violante
    14th IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2008.47

  22. On the generation of test programs for chip multithread computer architectures
    D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE International Test Conference (ITC)
    DOI: 10.1109/TEST.2008.4700678

  23. RFID for agri-food traceability: methods for authentication, integrity and privacy
    C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, E. Sanchez

  24. Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA
    M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, D. Merodio Codinachs, S. Pastore, G. Sorrenti, L. Sterpone, R. Weigand, M. Violante
    DOI: 10.1109/RADECS.2008.5782703

  25. SoC Symbolic Simulation: a case study on delay fault testing
    Bosio, A, P. Girard, S. Pravossoudovich, P. Bernardi
    DOI: 10.1109/DDECS.2008.4538810

  26. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
    W. Perez, J. Velasco Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda