1. A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    9th International Workshop on Microprocessor Test and Verification (MTV'08)
    DOI: 10.1109/MTV.2008.9

  2. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
    M. Sonza Reorda, M. Violante, C. Meinhardt, R. Reis
    Design, Automation & Test in Europe Conference & Exhibition (DATE '09)

  3. A low-cost solution for developing reliable Linux-based space computers for on-board data handling
    M. Violante, M. Esposti
    DOI: 10.1109/IOLTS.2009.5195982

  4. A new RC design for mixed-grain based dynamically reconfigurable architectures
    E. Rhod, L. Sterpone, L. Carro
    IEEE International Conference on Electronics Circuits and Systems
    DOI: 10.1109/ICECS.2009.5410843

  5. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    F. Abate, F. Lima Kastensmidt, L. Sterpone, M. Violante

  6. An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs
    L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
    12th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS)

  7. An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs
    D. Appello, P. Bernardi, C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, F. Piazza
    IEEE Internation On-Line Test Symposium (IOLTS'09)
    DOI: 10.1109/IOLTS.2009.5195977

  8. An In-Vehicle Infotainment Software Architecture Based on Google Android
    G. Macario, M. Torchiano, M. Violante
    IEEE Symposium on Industrial Embedded Systems (SIES) 2009
    DOI: 10.1109/SIES.2009.5196223
    ABSTRACT: The automotive infotainment industry is currently pressured with many challenges. Tier-one manufactures must accommodate disparate and quickly changing features for different carmakers. Moreover, the use of a dedicated platform for each brand and model is no more viable. The use of an open platform would permit sharing costs across the whole customer spectrum, and it will allow products to grow and adapt to the user preferences, by providing the possibility of executing third-party applications. Google Android is a recent operating system, designed for mobile devices that perfectly fits to embedded devices such as those used for automotive infotainment. In this paper we present a proof-of-concept architecture developed in cooperation between Magneti Marelli and Politecnico di Torino, whose main contribution is an automotive-oriented extension of Google Android that provides features for combining extendibility and safety requirements

  9. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs
    M. Sonza Reorda, M. Violante, C. Meinhardt
    24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009 (DFT09)
    DOI: 10.1109/DFT.2009.35

  10. An efficient fault simulation technique for transition faults in non-scan sequential circuits
    A. Bosio, P. Girard, S. Pravossoudovich, P. Bernardi, M. Sonza Reorda
    Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
    DOI: 10.1109/DDECS.2009.5012098
    ABSTRACT: This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques

  11. An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs
    L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
    DOI: 10.1109/DDECS.2009.5012141
    KEYWORDS: fpga based tester; test compression/decompression

  12. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs
    N. Battezzati, F. Decuzzi, M. Violante, M. Briet
    Proceedings of the 15th IEEE International On-Line Testing Symposium

  13. Automatic Detection of Software Defects: an Industrial Experience
    S. Gandini, D. Ravotto, W. Ruzzarin, E. Sanchez, G. Squillero, A. Tonda
    Proceedings GECCO 2009

  14. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/ETS.2009.16

  15. Curricula design flow with embedded accreditation
    D. Del Corso, M. Gola, M. Rebaudengo
    DOI: 10.1109/EAEEIE.2009.5335480
    ABSTRACT: EAEEIE Annual Conference, Valencia, Spain, 22-24 June 2009

  16. Design validation of multithreaded architectures using concurrent threads evolution
    D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
    22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
    DOI: 10.1145/1601896.1601964

  17. DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
    D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
    27th IEEE VLSI Test Symposium (VTS '09)
    DOI: 10.1109/VTS.2009.26

  18. DiseƱo de placas con lógica programable como experiencia educativa en cursos de grado
    S. Fernández, A. Bergeret, L. Ciganda, J. Oliver
    Actas de las IX jornadas de computación reconfigurable y aplicaciones
    KEYWORDS: fpga

  19. Evaluating Alpha-induced Soft Errors in Embedded Microprocessors
    P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello, P. Rech, S. Gerardin, A. Paccagnella
    IEEE Internation On-Line Test Symposium (IOLTS'09)
    DOI: 10.1109/IOLTS.2009.5195985

  20. Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core
    P. Rech, A. Paccagnella, M. Grosso, M. Sonza Reorda, F. Melchiori, D. Appello
    DOI: 10.1109/RADECS.2009.5994699

  21. Exploiting Embedded FPGA in On-line Software-based Test Strategies for Microprocessor Cores
    M. Grosso, M. Sonza Reorda
    15th IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2009.5195989

  22. Gene expression reliability estimation through cluster-based analysis
    L. Sterpone, A. Benso, Di Carlo.S., G. Politano
    DOI: 10.1109/MEMEA.2009.5167990
    KEYWORDS: bioinformatics; gene expression; image analysis; cdna microarray
    ABSTRACT: Gene expression is the fundamental control of the structure and functions of the cellular versatility and adaptability of any organisms. The measurement of gene expressions is performed on images generated by optical inspection of microarray devices which allow the simultaneous analysis of thousands of genes. The images produced by these devices are used to calculate the expression levels of mRNA in order to draw diagnostic information related to human disease. The quality measures are mandatory in genes classification and in the decision-making diagnostic. However, microarrays are characterized by imperfections due to sample contaminations, scratches, precipitation or imperfect gridding and spot detection. The automatic and efficient quality measurement of microarray is needed in order to discriminate faulty gene expression levels. In this paper we present a new method for estimate the quality degree and the data's reliability of a microarray analysis. The efficiency of the proposed approach in terms of genes expression classification has been demonstrated through a clustering supervised analysis performed on a set of three different histological samples related to the Lymphoma's cancer disease

  23. Improving Preamble Sampling Performance in Wireless Sensor Networks with State Information
    E. Sanchez, C. Chaudet, M. Rebaudengo

  24. Introducing Probability in RFID Reader-to-Reader Anti-collision
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    The 8th IEEE International Symposium on Network Computing and Applications (IEEE NCA09)

  25. Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs
    L. Sterpone, M. Violante, A. Bocquillon, F. Miller, N. Buard, A. Manuzzato, S. Gerardin, A. Pacagnella
    DOI: 10.1109/RADECS.2009.5994561

  26. On the Generation of Functional Test Programs for the Cache Replacement Logic
    W. Perez H, D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda
    Asian Test Symposium, ATS'09

  27. Random Key Pre-Distribution with Transitory Master Key for Wireless Sensor Networks
    F. Gandino, B. Montrucchio, M. Rebaudengo
    CoNEXT Student Workshop'09

  28. Recovery scheme for hardening system on programmable chips
    C. Meinhardt, R. Reis, M. Violante, M. Sonza Reorda
    10th IEEE Latin American Test Workshop (LATW '09)
    DOI: 10.1109/LATW.2009.4813816

  29. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    proceedings of IEEE International Conference on Field Programmable Logic and Applications
    DOI: 10.1109/FPL.2009.5272321

  30. Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
    L. Sterpone
    Lecture Notes in Computer Science (vol 5453)
    DOI: 10.1007/978-3-642-00641-8_11
    ABSTRACT: Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Contrariwise the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from the signal processing to the networking. SRAM-based FPGA is the candidate device for achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA's functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29% on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA's configuration memory