1. A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
    M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, E. Sanchez, M. De Carvalho, M. Sonza Reorda
    DOI: 10.1109/ETS.2011.21

  2. A Low-cost Emulation System for Fast Co-verification and Debug
    J. Lagos-Benites, M. Grosso, L. Sterpone, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini
    DOI: 10.1109/ETS.2011.32
    KEYWORDS: verification; validation; fpga; soc

  3. A New Reconfigurable Clock-gating Technique for Low Power SRAM-based FPGAs
    L. Sterpone, D. Matos, L. Carro, S. Wong, F. Anjam

  4. A general approach for improving RNS Montgomery exponentiation using pre-processing
    F. Gandino, F. Lamberti, J. Bajard, P. Montuschi
    Proc. 20th IEEE Symposium on Computer Arithmetic (ARITH2011)
    DOI: 10.1109/ARITH.2011.35

  5. A new Architecture to Cross-Fertilize On-line and Manufacturing Testing
    P. Bernardi, M. Sonza Reorda

  6. A novel access scheme for online test in RFID memories
    R. Sanchez E.R.
    DOI: 10.1109/LASCAS.2011.5750307
    KEYWORDS: online test; rfid

  7. Adaptive fuzzy-MAC for power reduction in wireless sensor networks
    E. Sanchez, B. Montrucchio, L. Murillo, M. Rebaudengo
    DOI: 10.1109/NTMS.2011.5720629
    KEYWORDS: preamble sampling; fuzzy logic; wireless sensor networks; mac
    ABSTRACT: Wireless Sensor Networks (WSNs) are used in an increasing number of applications in different fields, from agricultural monitoring to energy-saving systems for buildings. The development of WSNs has been always constrained by the power consumption of nodes that constitute the network since they should be as much autonomous as possible and human intervention must be reduced to the minimum. Several algorithms and protocols have been designed with the goal of reducing power consumption. Related works take into consideration Media Access Control (MAC) protocols that keep sensors' power consumption low at that layer. Nevertheless, these protocols require some parameters, e.g. duty cycle, to be configured according to network characteristics in order to achieve an acceptable level of efficiency. In this work, we propose a Fuzzy Logic Controller (FLC) which adapts the MAC protocol parameters by employing local node inputs such as battery power and average packet traffic. We present the FLC design and perform simulations that show its feasibility. We evaluate the FLC in terms of its power savings capabilities and show that for high-traffic and low-energy nodes power consumption may be reduced up to 50%

  8. Adaptive opponent modelling for the iterated prisoner's dilemma
    E. Piccolo, G. Squillero
    DOI: 10.1109/CEC.2011.5949705
    ABSTRACT: This paper describes the design of Laran, an intelligent player for the iterated prisoner's dilemma. Laran is based on an evolutionary algorithm, but instead of using evolution as a mean to define a suitable strategy, it uses evolution to model the behavior of its adversary. In some sense, it understands its opponent, and then exploits such knowledge to devise the best possible conduct. The internal model of the opponent is continuously adapted during the game to match the actual outcome of the game, taking into consideration all played actions. Whether the model is correct, Laran is likely to gain constant advantages and eventually win. A prototype of the proposed approach was matched against twenty players implementing state-of-the art strategies. Results clearly demonstrated the claims

  9. An Effective Methodology for On-line Testing of Embedded Microprocessors
    P. Bernardi, L. Ciganda, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/IOLTS.2011.5994541
    KEYWORDS: on-line test; microprocessor test; hardware bist

  10. An FPGA-emulation-based platform for characterization of digital baseband communication systems
    J. Lagos-Benites, M. Grosso, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini, V. Avantaggiati
    DOI: 10.1109/DFT.2011.1

  11. An adaptive power-aware multi-hop routing algorithm for wireless sensor networks
    E. Sanchez, L. Murillo, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/ITNG.2011.27
    KEYWORDS: wireless sensor network; adaptive routing algorithm

  12. An adaptively reconfigurable computing framework for intelligent robotics
    M. Hussain, A. Din, M. Violante, B. Bona

  13. Analysis of SEU Effects in Partially Reconfigurable SoPCs
    L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, M. Porrman
    DOI: 10.1109/AHS.2011.5963926

  14. Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification2011 12th International Workshop on Microprocessor Test and Verification
    E. Sanchez, G. Squillero, A. Tonda
    2011 12th International Workshop on Microprocessor Test and Verification
    DOI: 10.1109/MTV.2011.19
    ABSTRACT: The 40 years since the appearance of the Intel 4004 deeply changed how microprocessors are designed. Today, essential steps in the validation process are performed relying on physical dices, analyzing the actual behavior under appropriate stimuli. This paper presents a methodology that can be used to devise assembly programs suitable for a range of on-silicon activities, like speed debug, timing verification or speed binning. The methodology is fully automatic. It exploits the feedback from the microprocessor under examination and does not rely on information about its microarchitecture, nor does it require design-for-debug features. The experimental evaluation performed on a Intel Pentium Core i7-950 demonstrates the feasibility of the approach

  15. Control flow checking through embedded debug interface
    L. Parra, A. Lindoso, M. Portela, L. Entrena, M. Grosso, M. Sonza Reorda

  16. Covariance Matrix Adaptation Evolutionary Strategy for Drift Correction of Electronic Nose Data
    S. Di Carlo, M. Falasconi, E. Sanchez, G. Sberveglieri, A. Scionti, G. Squillero, A. Tonda
    DOI: 10.1063/1.3626293
    KEYWORDS: sensor drift; data acquisition; optimisation; self-organising feature maps; chemical sensors; pattern recognition; bioinformatics
    ABSTRACT: Electronic Noses (ENs) might represent a simple, fast, high sample throughput and economic alternative to conventional analytical instruments. However, gas sensors drift still limits the EN adoption in real industrial setups due to high recalibration effort and cost. In fact, pattern recognition (PaRC) models built in the training phase become useless after a period of time, in some cases a few weeks. Although algorithms to mitigate the drift date back to the early 90 this is still a challenging issue for the chemical sensor community. Among other approaches, adaptive drift correction methods adjust the PaRC model in parallel with data acquisition without need of periodic calibration. Self-Organizing Maps (SOMs) and Adaptive Resonance Theory (ART) networks have been already tested in the past with fair success. This paper presents and discusses an original methodology based on a Covariance Matrix Adaptation Evolution Strategy (CMA-ES), suited for stochastic optimization of complex problems

  17. Degree Distribution of Unit Disk Graphs with Uniformly Deployed Nodes on a Rectangular Surface
    F. R. Ferrero
    DOI: 10.1109/BWCCA.2011.38
    KEYWORDS: wireless network modeling; degree distribution; unit disk graph

  18. Efficient energy-aware routing for sensor networks
    E. Sanchez, L. Murillo, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/LASCAS.2011.5750315
    KEYWORDS: wireless sensor networks; energy-aware; routing protocols
    ABSTRACT: The energy and computational constraints of Wireless Sensor Networks (WSN) have motivated the exploration of efficient routing algorithms. In this paper, a new routing approach is presented which attains the best trade-off between energy expenditure and hop-distance to the sink. The routing algorithm exploits a low-computation metric based on the node's remaining battery. Routing is performed by means of a modified Dijkstra's algorithm which calculates the node's position in the routing tree while computes the least-cost path of all nodes towards the sink. Simulations were performed for different network densities demonstrating that the proposed algorithm enhances the overall energy conservation of the network while efficiently routing data traffic

  19. Evaluation Framework of Opportunistic Flooding in Wireless Sensor Networks
    L. Zhang, E. Sanchez Sanchez, M. Rebaudengo

  20. Evolution of Test Programs Exploiting a FSM Processor Model
    E. Sanchez, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 6625)
    DOI: 10.1007/978-3-642-20520-0_17
    ABSTRACT: Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs. A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to time-expensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault model

  21. Evolutionary failing-test generation for modern microprocessors
    E. Sanchez, G. Squillero, A. Tonda
    GECCO '11 Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
    DOI: 10.1145/2001858.2001985
    ABSTRACT: The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Nowadays, comprehensive verification of a chip can only be performed after tape-out, when the first silicon prototypes are available. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating to this post-silicon time as well. The short paper describes a post-silicon methodology that can be exploited to devise functional failing tests. Such tests are essential to analyze and debug speed paths during verification, speed-stepping, and other critical activities. The proposed methodology is based on the Genetic Programming paradigm, and exploits a versatile toolkit named µGP. The paper demonstrates that an evolutionary algorithm can successfully tackle a significant and still open industrial problem. Moreover, it shows how to take into account complex hardware characteristics and architectural details of such complex devices

  22. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda

  23. Fault grading of software-based self-test procedures for dependable automotive applications
    P. Bernardi, M. Grosso, E. Sanchez, O. Ballan

  24. Functional test generation for the pLRU replacement mechanism of embedded cache memories
    W. Perez Holgin, E. Sanchez, M. Sonza Reorda, A. Tonda, J. Velasco-Medina
    DOI: 10.1109/LATW.2011.5985898
    ABSTRACT: Testing cache memories is a challenging task, especially when targeting complex and high-frequency devices such as modern processors. While the memory array in a cache is usually tested exploiting BIST circuits that implement March-based solutions, there is no established methodology to tackle the cache controller logic, mainly due to its limited accessibility. One possible approach is Software-Based Self Testing (SBST): however, devising test programs able to thoroughly excite the replacement logic and made the results observable is not trivial. A test program generation approach, based on a Finite State Machine (FSM) model of the replacement mechanism, is proposed in this paper. The effectiveness of the method is assessed on a case study considering a data cache implementing the pLRU replacement policy

  25. Group evolution: Emerging synergy through a coordinated effort
    E. Sanchez, G. Squillero, A. Tonda
    Evolutionary Computation (CEC), 2011 IEEE Congress on
    DOI: 10.1109/CEC.2011.5949951
    ABSTRACT: Abstract-A huge number of optimization problems, in the CAD area as well as in many other fields, require a solution composed by a set of structurally homogeneous elements. Each element tackles a subset of the original task, and they cumulatively solve the whole problem. Sub-tasks, however, have exactly the same structure, and the splitting is completely arbitrary. Even the number of sub-tasks is not known and cannot be determined a-priori. Individual elements are structurally homogeneous, and their contribution to the main solution can be evaluated separately. We propose an evolutionary algorithm able to optimize groups of individuals for solving this class of problems. An individual of the best solution may be sub-optimal when considered alone, but the set of individuals cumulatively represent the optimal group able to completely solve the whole problem. Results of preliminary experiments show that our algorithm performs better than other techniques commonly applied in the CAD field

  26. Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor
    J. Perez Acle, M. Sonza Reorda, M. Violante
    DOI: 10.1109/LASCAS.2011.5750278

  27. Increasing Throughput in RFID Multi-Reader Environments Avoiding Reader-to-Reader Collisions
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/ICCE.2011.5722638
    KEYWORDS: rfid; reader-to-reader collision

  28. La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti
    S. Barbagallo, R. Bertonasco, F. Corno, M. Mezzalama, M. Sonza Reorda, E. Venuto

  29. Lamps: A Test Problem for Cooperative Coevolution
    A. Tonda, E. Lutton, G. Squillero
    Nature Inspired Cooperative Strategies for Optimization
    DOI: 10.1007/978-3-642-24094-2_7
    ABSTRACT: We present an analysis of the behaviour of Cooperative Co-evolution algorithms (CCEAs) on a simple test problem, that is the optimal placement of a set of lamps in a square room, for various problems sizes. Cooperative Co-evolution makes it possible to exploit more efficiently the artificial Darwinism scheme, as soon as it is possible to turn the optimisation problem into a co-evolution of interdependent sub-parts of the searched solution. We show here how two cooperative strategies, Group Evolution (GE) and Parisian Evolution (PE) can be built for the lamps problem. An experimental analysis then compares a classical evolution to GE and PE, and analyses their behaviour with respect to scale

  30. Monitoring and modeling building energy expenditure with sensor networks
    E. Sanchez, B. Montrucchio, M. Rebaudengo

  31. On the Functional Test of Branch Prediction Units based on Branch History Table
    E. Sanchez, M. Sonza Reorda, A. Tonda

  32. On the Modeling of Gate Delay Faults by Means of Transition Delay Faults
    P. Bernardi, M. Sonza Reorda, A. Bosio, P. Girard, S. Pravossoudovitch
    DOI: 10.1109/DFT.2011.53

  33. On the functional test of MESI controllers
    M. Ernesto Sanchez
    DOI: 10.1109/LATW.2011.5985909

  34. Optimized embedded memory diagnosis
    M. De Carvalho, P. Bernardi, M. Sonza Reorda, N. Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, M. Terzi
    DOI: 10.1109/DDECS.2011.5783109

  35. Performance Evaluation of Reliable and Unreliable Opportunistic Flooding in Wireless Sensor Network
    L. Zhang, E. Sanchez Sanchez, M. Rebaudengo
    DOI: 10.1109/ICON.2011.6168498

  36. Post-silicon failing-test generation through evolutionary computation
    E. Sanchez, G. Squillero, A. Tonda
    DOI: 10.1109/VLSISoC.2011.6081667
    ABSTRACT: The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating after tape-out, when the first silicon prototypes are available. The paper describes a post-silicon methodology for devising functional failing tests. Therefore, suited to be exploited by microprocessor producer to detect, analyze and debug speed paths during verification, speed-stepping, or other critical activities. The proposed methodology is based on an evolutionary algorithm and exploits a versatile toolkit named µGP. The paper describes how to take into account complex hardware characteristics and architectural details of such complex devices. The experimental evaluation clearly demonstrates the potential of this line of research