Publications

  1. A Comparison between Single and Additive Contribution in RFID Reader-to-Reader Interference Models
    L. Zhang, R. Ferrero, F. Gandino, M. Rebaudengo
    DOI: 10.1109/IMIS.2012.122
    KEYWORDS: reader-to-reader collision; rfid; interference models
    ABSTRACT: The RFID reader-to-reader collision is a wellknown interference problem that affects large RFID systems with many readers. In recent years, several anti-collision protocols have been proposed in order to address this problem. However, the evaluation of these approaches is often based on simple models that consider only direct collisions among two readers. Instead, more complex models capture the total signal power emitted by each reader and assume that the power of each signal decays as distance grows. In this paper, the main models of the two families are described, and a comparison is presented, in order to investigate their effectiveness for the study and the evaluation of reader-to-reader collision

  2. A New Fault Injection Approach for Testing Network-on-Chips
    L. Sterpone, D. Sabena, M. Sonza Reorda
    DOI: 10.1109/PDP.2012.82
    ABSTRACT: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault tolerance capability of NoCs. This paper presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows to investigate the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale NoC design

  3. A New SBST Algorithm for Testing the Register File of VLIW Processors
    L. Sterpone, D. Sabena, M. Sonza Reorda

  4. A SBST strategy to test microprocessors' branch target buffer
    P. Bernardi, L. Ciganda, M. Grosso, E. Sanchez, M. Sonza Reorda
    KEYWORDS: testing, microprocessors, branch prediction, sbst, branch target buffer
    ABSTRACT: A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the causes for low functional testability and propose some techniques able to effectively face these issues. In particular, we describe a strategy to perform SBST on fully associative BTB units. The unit's general structure is analyzed, a suitable test program is proposed and the strategy to observe the test responses is explained. Feasibility and effectiveness of the proposed approach are shown on a MIPS-like processor

  5. A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories
    E. Costenaro, M. Violante, D. Alexandrescu
    DOI: 10.1109/IOLTS.2011.5993810

  6. A scalable platform for run-time reconfigurable satellite payload processing
    J. Hagemeyer, A. Hilgenstein, D. Jungewelter, D. Cozzi, C. Felicetti, U. Rueckert, S. Korf, M. Koester, F. Margaglia, M. Porrmann, F. Dittmann, M. Ditze, J. Harris, L. Sterpone, J. Ilstad
    DOI: 10.1109/AHS.2012.6268642
    KEYWORDS: fpga; fault tolerance; reconfiguration

  7. Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs
    C. Bernardeschi, L. Cassano, A. Domenici, L. Sterpone
    DOI: 10.1109/DFT.2012.6378210
    KEYWORDS: fault tolerance; seu; fpga

  8. An hybrid architecture to detect transient faults in microprocessors: An experimental validation
    V. Campagna S.
    ABSTRACT: Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures are needed. In this paper we present an in-depth experimental evaluation of a hybrid architecture to detect transient faults affecting microprocessors. The architecture leverages an hypervisor-based task-level redundancy scheme that operates in conjunction with a custom-developed hardware module. The experimental evaluation shows that our lightweight redundancy scheme is able to effectively cope with malicious faults as those affecting the pipeline of a RISC microprocessor

  9. Automatic Generation of On-Line Test Programs through a Cooperation Scheme
    L. Ciganda, M. Gaudesi, E. Lutton, E. Sanchez, G. Squillero, A. Tonda
    DOI: 10.1109/MTV.2012.17
    KEYWORDS: group evolution; software-based self-test; on-line testing; pipelined processors; soc
    ABSTRACT: Test programs for Software-based Self-Test (SBST) can be exploited during the mission phase of microprocessor-based systems to periodically assess hardware integrity. However, several additional constraints must be imposed due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST on-line test programs for embedded RISC processors, systems where the impact of on-line constraints is significant. The proposed strategy exploits an evolutionary optimizer that is able to create a complete test set of programs relying on a new cooperative scheme. Experimental results showed high fault coverage values on two different modules of a MIPS-like processor core. These two case studies demonstrate the effectiveness of the technique and the low human effort required for its implementation

  10. Evaluation of the Additive Interference Model for RFID Reader Collision Problem
    L. Zhang, F. Gandino, R. Ferrero, M. Rebaudengo
    KEYWORDS: reader-to-reader collision; interference models; rfid
    ABSTRACT: The reader collision problem is a critical issue in RFID systems, since it affects the reliability and the efficiency of the network. Although several solutions have been proposed to address the reader collision problem, they are usually based on models that consider only direct collisions among two readers. In real deployments, the additive interference model that captures the accumulation of n concurrent readers' interference is more accurate. Furthermore, even if an additive interference model is considered, it is important to decide how many concurrent readers' interferences have to be considered. The value of n determines a trade-off between the reliability and the efficiency of the RFID system. In this paper, the additive interference model with different values of n is evaluated. The proposed model provides an evaluation tool to select a suitable value of n according to the system requirements and the simulation results have shown the impact of n in a specific deployment

  11. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
    C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omana, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella
    DOI: 10.1109/DFT.2012.6378211
    ABSTRACT: This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section

  12. Latch-up test measurement for long duration space missions
    L. Sterpone, R. Mancini, D. Gelfusa
    DOI: 10.1109/I2MTC.2012.6229561
    KEYWORDS: asic latch-up; radiation; test

  13. On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture
    E. Sanchez, M. Sonza Reorda, A.P. Tonda
    VLSI-SoC: Advanced Research for Systems on Chip 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers
    DOI: 10.1007/978-3-642-32770-4
    ABSTRACT: Branch Prediction Units (BPUs) are commonly used in pipelined processors, since they can significantly decrease the negative impact of branches in superscalar and RISC architectures. Traditional solutions, mainly based on scan, are often inadequate to effectively test these modules: in particular, scan does not represent a viable solution when Incoming Inspection or on-line test are considered. Functional test may stand as an effective solution in these situations, but requires effective algorithms to be available. In this paper we propose a functional approach targeting the test of BPUs based on the Branch History Table (BHT) architecture; the proposed approach is independent on the specific implementation of the BPU, and is thus widely applicable. Its effectiveness has been validated on a BPU resorting to an open-source computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BPU, reaching complete static fault coverage with reasonable requirements in terms of test program size and execution time

  14. On the development of Software-Based Self-Test methods for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    DOI: 10.1109/DFT.2012.6378194
    KEYWORDS: vliw; fault simulation; sbst
    ABSTRACT: Software-Based Self-Test (SBST) approaches are an effective solution for detecting permanent faults; this technique has been widely used with a good success on generic processors and processors-based architectures; however, when VLIW processors are addressed, traditional SBST techniques and algorithms must be adapted to each particular VLIW architecture. In this paper, we present a method that formalizes the development flow to write effective SBST programs for VLIW processors, starting from known algorithms addressing traditional processors. In particular, the method addresses the parallel Functional Units, such as ALUs and MULs, embedded into a VLIW processor. Fault simulation campaigns confirm the validity of the proposed method

  15. On the functional test of L2 caches
    M. Riga, E. Sanchez, M. Sonza Reorda
    KEYWORDS: sbst; functional testing; l2 cache testing
    ABSTRACT: Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor

  16. On the optimized generation of Software-Based Self-Test programs for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    DOI: 10.1109/VLSI-SoC.2012.6379018
    KEYWORDS: test program generation; sbst; vliw
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this paper we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while reducing the test duration and the test code size. The method consists of three parametric phases and can deal with different VLIW processor models. The main goal of the proposed method is to automatically obtain a test program able to effectively reduce the test time and the required resources. Experimental results gathered on a case study show the effectiveness of the proposed approach

  17. On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors
    P. Bernardi, L. Ciganda, M. De Carvalho, M. Grosso, J. Lagos-Benites, E. Sanchez, M. Sonza Reorda, O. Ballan

  18. On-line test of embedded systems: Which role for functional test?
    M. Sonza Reorda
    DOI: 10.1109/DDECS.2012.6219007

  19. Peak Power Estimation: A Case Study on CPU Cores
    P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L. Dilillo, P. Girard, M. Valka
    DOI: 10.1109/ATS.2012.58

  20. SEU effects on power consumption in FPGAs
    A. Aloisio, V. Bocci, G. Chiodi, R. Giordano, V. Izzo, L. Sterpone, M. Violante
    DOI: 10.1109/RTC.2012.6418110
    KEYWORDS: power consumption; fpga; seu