1. A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors
    P. Bernardi, D. Boyang, L. Ciganda, E. Sanchez, M. Sonza Reorda, M. Grosso, O. Ballan
    IEEE 7th International Design and Test Symposium (IDT)
    DOI: 10.1109/IDT.2013.6727120
    ABSTRACT: When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RF&PI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RF&PI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power Architecture

  2. A Memetic Approach to Bayesian Network Structure Learning
    A. Tonda, E. Lutton, G. Squillero, Pierre-Henri Wuillemin
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-642-37192-9_11
    KEYWORDS: memetic algorithms; evolutionary algorithms; local optimization; bayesian networks; model learning
    ABSTRACT: Bayesian networks are graphical statistical models that represent inference between data. For their effectiveness and versatility, they are widely adopted to represent knowledge in different domains. Several research lines address the NP-hard problem of Bayesian network structure learning starting from data: over the years, the machine learning community delivered effective heuristics, while different Evolutionary Algorithms have been devised to tackle this complex problem. This paper presents a Memetic Algorithm for Bayesian network structure learning, that combines the exploratory power of an Evolutionary Algorithm with the speed of local search. Experimental results show that the proposed approach is able to outperform state-of-the-art heuristics on two well-studied benchmarks

  3. Accounting for Post-Transcriptional Regulation in Boolean Networks Based Regulatory Models
    A. Benso, S. Di Carlo, H. Rehman, G. Politano, A. Savino, G. Squillero, A. Vasciaveo, S. Benedettini
    International Work-Conference on Bioinformatics and Biomedical Engineering (IWBBIO) 2013
    KEYWORDS: mirna; gene regulatory networks; post-transcriptional regulation; boolean networks; complex systems; network analysis; bioinformatics
    ABSTRACT: Boolean Networks are emerging as a simple yet powerful for- malism to model and study Gene Regulatory Networks. Nevertheless, the most widely used Boolean Network-based models do not include any post-transcriptional regulation mechanism. In this paper we discuss how the post-transcriptional regulation mechanism mediated by miRNAs can be included in a Boolean Network based model to have a more realistic representation of a Gene Regulatory Networks. This contribution con- stitutes a critical preparatory step in the study of the topological and structural role of miRNAs in complex regulatory networks

  4. Accurate Mitigation of Single Event Effects on Flash-based FPGAs: A new Design Flow
    L. Sterpone, B. Du, D. Merodio Codinachs, V. Ferlet Cavrois
    Proceedings of RADECS
    KEYWORDS: fpga; single event transients (sets)
    ABSTRACT: We propose a new design flow for implementing circuits hardened against SET effects af- fecting Flash-based FPGAs. Experimental results on RISC microprocessors show an in- crease of robustenss of more than 70% wrt traditional mitigation approaches

  5. An Efficient Distance Metric for Linear Genetic Programming
    M. Gaudesi, G. Squillero, A. Tonda
    Proceeding of the fifteenth annual conference on Genetic and evolutionary computation conference
    DOI: 10.1145/2463372.2463495
    KEYWORDS: measurement; algorithms
    ABSTRACT: Defining a distance measure over the individuals in the population of an Evolutionary Algorithm can be exploited for several applications, ranging from diversity preservation to balancing exploration and exploitation. When individuals are encoded as strings of bits or sets of real values, computing the distance between any two can be a straightforward process; when individuals are represented as trees or linear graphs, however, quite often the user must resort to phenotype-level problem-specific distance metrics. This paper presents a generic genotype-level distance metric for Linear Genetic Programming: the information contained by an individual is represented as a set of symbols, using n-grams to capture significant recurring structures inside the genome. The difference in information between two individuals is evaluated resorting to a symmetric difference. Experimental evaluations show that the proposed metric has a strong correlation with phenotype-level problem-specific distance measures in two problems where individuals represent string of bits and Assembly-language programs, respectively

  6. An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems
    M. Sonza Reorda, L. Sterpone, A. Ullah

  7. An Evolutionary Approach to Wetlands Design
    M. Gaudesi, A. Marion, T. Musner, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 7833)
    DOI: 10.1007/978-3-642-37189-9_16
    KEYWORDS: evolutionary algorithms; wetlands design; ecological modelling
    ABSTRACT: Wetlands are artificial basins that exploit the capabilities of some species of plants to purify water from pollutants. The design process is currently long and laborious: such vegetated areas are inserted within the basin by trial and error, since there is no automatic system able to maximize the efficiency in terms of filtering. Only at the end of several attempts, experts are able to determine which is the most convenient configuration and choose up a layout. This paper proposes the use of an evolutionary algorithm to automate both the placement and the sizing of vegetated areas within a basin. The process begins from a random population of solutions and, evaluating their efficiency with an state-of-the-art fluid-dynamics simulation framework, the evolutionary algorithm is able to automatically find optimized solution whose performance are comparable with those achieved by human experts

  8. An Evolutionary Framework for Routing Protocol Analysis in Wireless Sensor Networks
    D. Bucur, G. Iacca, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 7835)
    DOI: 10.1007/978-3-642-37192-9-1
    ABSTRACT: Wireless Sensor Networks (WSNs) are widely adopted for applications ranging from surveillance to environmental monitoring. While powerful and relatively inexpensive, they are subject to behavioural faults which make them unreliable. Due to the complex interactions between network nodes, it is difficult to uncover faults in a WSN by resorting to formal techniques for verification and analysis, or to testing. This paper proposes an evolutionary framework to detect anomalous behaviour related to energy consumption in WSN routing protocols. Given a collection protocol, the framework creates candidate topologies and evaluates them through simulation on the basis of metrics measuring the radio activity on nodes. Experimental results using the standard Collection Tree Protocol show that the proposed approach is able to unveil topologies plagued by excessive energy depletion over one or more nodes, and thus could be used as an offline debugging tool to understand and correct the issues before network deployment and during the development of new protocols

  9. An efficient method for the test of embedded memory cores during the operational phase
    P. Bernardi, L. Ciganda, M. Sonza Reorda, S. Hamdioui
    2013 22nd Asian Test Symposium
    ABSTRACT: System on Chip devices include an increasing number of embedded memory cores, whose test during the operational phase is often a strict requirement, especially for safety-critical applications. This paper proposes a new memory test method combining the characteristics of hardware and software solutions: the test is performed by the microcontroller/processor, while the code of the test instructions to be executed is generated on-the-fly by an ad hoc module, also in charge of checking the memory behavior. The solution is modular and does not require any modification either in the memory cores or in the processor. Moreover, it is well suited to be used for test during the operational phase. Experimental results, gathered by implementing some representative March elements and algorithms, show that the method guarantees higher defect coverage than software BIST and a test time comparable with that of traditional hardware BIST solutions with a reduced hardware cost

  10. Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture
    L. Sterpone, D. Sabena, A. Ullah, M. Porrmann, J. Hagemeyer, J. Ilstad

    B. Du, M. Sonza Reorda, L. Sterpone, L. Parra, M. Portela Garcia, A. Lindoso, L. Entrena
    DOI: 10.1109/IOLTS.2013.6604058

  12. Evolutionary Optimization of Wetlands Design
    M. Gaudesi, A. Marion, T. Musner, G. Squillero, A. Tonda
    Proceedings of the 28th Annual ACM Symposium on Applied Computing
    DOI: 10.1145/2480362.2480400
    KEYWORDS: wetlands design; evolutionary algorithms; optimization
    ABSTRACT: Wetlands are artificial ponds, designed to filter and purify running water through the contact with plant stems and roots. Wetland layouts are traditionally designed by experts through a laborious and time-consuming procedure: in principle, small patches of vegetation with purifying properties are tentatively placed, then the resulting water flow is verified by fluid dynamics simulators and when a satisfying outcome is reached, the wetland final layout is decided. This paper proposes to automate wetland design exploiting an evolutionary algorithm: a population of candidate solutions is cultivated by the evolutionary core, and their efficiency is evaluated using a state-of-the-art fluid-dynamics simulation framework. Experimental results show that the results obtained by the proposed approach are qualitatively comparable with those provided by experts, despite the complete absence of human intervention during the optimization process

  13. Fault detection in RNS Montgomery modular multiplication
    J. Jean-Claude Bajard, F. Gandino
    DOI: 10.1109/ARITH.2013.31
    KEYWORDS: base conversions; fault detection; montgomery reduction; rns
    ABSTRACT: Recent studies have demonstrated the importance of protecting the hardware implementations of cryptographic functions against side channel and fault attacks. In last years, very efficient implementations of modular arithmetic have been done in RNS (RSA, ECC, pairings) as well on FPGA as on GPU. Thus the protection of RNS Montgomery modular multiplication is a crucial issue. For that purpose, some techniques have been proposed to protect this RNS operation against side channel analysis. Nevertheless, there are still no effective and generic approaches for the detection of fault injection, which would be additionnally compatible with a leak resistant arithmetic. This paper proposes a new RNS Montgomery multiplication algorithm with fault detection capability. A mathematical analysis demonstrates the validity of the proposed approach. Moreover, an architecture that implements the proposed algorithm is presented. A comparative analysis shows that the introduction of the proposed fault detection technique requires only a limited increase in area

  14. Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus
    A. Vaskova, M. Portela-Garcia, M. Garcia-Valderas, C. Lopez-Ongil, M. Sonza Reorda
    DOI: 10.1109/IOLTS.2013.6604044

  15. Hierarchical Key Negotiation Technique for Transitory Master Key Schemes in Wireless Sensor Networks
    C. Celozzi, F. Gandino, M. Rebaudengo
    KEYWORDS: key management; wireless sensor network; transitory master key
    ABSTRACT: Wireless sensor networks have been applied in various contexts where hardware and network data are exposed to security threats, such as tampering or eavesdropping. The majority of the security approaches adopted in this context are based on symmetric encryption, which requires keys shared among the nodes. Many key management schemes, like the transitory master key scheme LEAP+, have been proposed for the negotiation of keys. In this paper a new key negotiation technique suitable for LEAP+ protocol is described. The proposed protocol significantly reduces the time of exposition of sensitive information through a new organization of handshake operations and of key establishment. A comparison with the original version of LEAP+ was performed to evaluate the improvements achieved by the proposed approach

  16. Improving Key Negotiation in Transitory Master Key Schemes for Wireless Sensor Networks
    C. Celozzi, F. Gandino, M. Rebaudengo
    DOI: 10.1007/978-3-319-04166-7_1
    KEYWORDS: key management; wireless sensor networks; transitory master key
    ABSTRACT: In recent years, wireless sensor networks have been adopted in different areas of daily life, exposing the network data and the hardware to different security threats. Many key management schemes have been proposed aiming at securing the communications among nodes, for instance the popular LEAP+ protocol. This paper proposes an enhanced variant of the LEAP+ protocol that decreases the key setup time through the reduction of the number of exchanged packets thus improving the security of communications. The results extracted from extensive test sessions obtained by network simulation have been compared to the corresponding data derived from the LEAP+ protocol in order to quantify the improvements

  17. Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS)
    M. De Carvalho, P. Bernardi, E. Sanchez, M. Sonza Reorda, O. Ballan
    2013 IEEE 19th International On-Line Testing Symposium (IOLTS)
    DOI: 10.1109/IOLTS.2013.6604049

  18. Industrial applications of evolutionary algorithms
    G. Squillero
    Proceeding of the fifteenth annual conference companion on Genetic and evolutionary computation conference companion - GECCO '13 Companion
    DOI: 10.1145/2464576.2480814

  19. On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors
    D. Sabena, L. Sterpone, M. Sonza Reorda
    VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
    DOI: 10.1007/978-3-642-45073-0_9
    KEYWORDS: fault simulation; fault diagnosis; vliw processor; sbst
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach

  20. On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors
    S. Di Carlo, E. Sanchez, M. Sonza Reorda
    Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems 2013
    DOI: 10.1109/DDECS.2013.6549785
    KEYWORDS: microprocessor testing; software-based self-test; embedded memory test; on-line test; reorder buffer; digital system design test and verification
    ABSTRACT: The Reorder Buffer (ROB) is a key component in superscalar processors. It enables both in-order commitment of instructions and precise exception management even in those architectures that support out-of-order execution. The ROB architecture typically includes a memory array whose size may reach several thousands of bits. Testing this array may be important to guarantee the correct behavior of the processor. Proprietary BIST solutions typically adopted by manufacturers for end-of-production test are not always suitable for on-line test. In fact, they require the usage of test infrastructures that may be expensive, or may not be accessible and/or documented. This paper proposes an alternative solution, based on a functional approach, which has been validated resorting to both an architectural and a memory fault simulator

  21. On the Optimal Reconfiguration Times for TMR Circuits on SRAM based FPGAs
    L. Sterpone, A. Ullah

  22. On the development of diagnostic test programs for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    Proceedings of 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
    KEYWORDS: software-based fault diagnosis; fault simulation; vliw processors; software-based self-test
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. When partial reconfiguration is adopted to deal with permanent faults, we also need to identify the faulty module, which is then substituted with a spare one. Software-based Diagnosis techniques can be exploited for this purpose, too. When Very Long Instruction Word (VLIW) processors are addressed, these techniques can effectively exploit the parallelism intrinsic in these architectures. In this paper we propose a new approach that starting from existing detection-oriented programs generates a diagnosis-oriented test program which in most cases is able to identify the faulty module. Experimental results gathered on a case study show the effectiveness of the proposed approach

  23. On the evaluation of soft-errors detection techniques for GPGPUs
    D. Sabena, M. Sonza Reorda, L. Sterpone, P. Rech, L. Carro
    Proceedings of 2013 8th IEEE International Design and Test Symposium (IDT)
    KEYWORDS: soft errors; redundancy techniques; radiation testing; gpgpu
    ABSTRACT: Recently, General Purpose Graphic Processing Units (GPGPUs) have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, due to their complexity GPGPUs also show a relatively high sensitivity to soft errors. Hence, there is some interest in devising and applying software techniques able to exploit their computational power by just acting on the executed code. In this paper we report some preliminary results obtained by applying two different software redundancy techniques aimed at soft-error detection; these techniques are completely algorithm independent, and have been applied on a sample application running on a Commercial-Off-The-Shelf GPGPU. The results have been gathered resorting to a neutron testing campaign. Some experimental results, explaining the capabilities of the methods, are presented and commented

  24. On the functional test of the BTB logic in pipelined and superscalar processors
    D. Changdao, M. Graziano, E. Sanchez, M. Sonza Reorda, M. Zamboni, N. Zhifan
    Test Workshop (LATW), 2013 14th Latin American
    DOI: 10.1109/LATW.2013.6562677
    KEYWORDS: test program generation; branch prediction unit; sbst; branch target buffer
    ABSTRACT: Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB

  25. On-line functionally untestable fault identification in embedded processor cores
    P. Bernardi, M. Bonazza, E. Sanchez, M. Sonza Reorda, O. Ballan

  26. On-line testing of permanent radiation effects in reconfigurable systems
    L. Cassano, D. Cozzi, S. Korf, J. Hagemeyer, M. Porrmann, L. Sterpone
    DOI: 10.7873/DATE.2013.154

  27. Reliability Analysis Reloaded: How Will We Survive?
    R. Aitken, Görschwin Fey, T. Zbigniew, F. Reichenbach, M. Sonza Reorda
    ABSTRACT: In safety related applications and in products with long lifetimes reliability is a must. Moreover, facing future technology nodes of integrated circuit device level reliability may decrease, i.e., counter-measures have to be taken to ensure product level reliability. But assessing the reliability of a large system is not a trivial task. This paper revisits the state-of-the-art in reliability evaluation starting from the physical device level, to the software system level, all the way up to the product level. Relevant standards and future trends are discussed

  28. Simulating reader-to-reader interference in RFID systems
    R. Ferrero, F. Gandino, L. Zhang, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/WAINA.2013.90
    KEYWORDS: topology; rfid; reader-to-reader interference; anti-collision protocol; mobility model; network modeling
    ABSTRACT: Reader-to-reader interference significantly affects the performance of RFID applications. The design of an RFID system should carefully consider this phenomenon. Simulation can dramatically speed up the design and testing phase, by deferring the implementation of a prototype to the last phase of the development. Unfortunately, no specific simulators of interference in RFID networks are currently available. Previous works exploited either general purpose network simulators, which often do not provide the required features for simulating an RFID network, or self deployed tools, which are not publicly available and therefore do not allow the validation and reproducibility of the results. This paper identifies the requirements that a simulator of reader-to-reader interference should satisfy and presents the R2RIS simulator, which has been specifically designed to evaluate the performance of reader-to reader anti-collision protocols

  29. Simulation and evaluation of the interference models for RFID reader-to-reader collisions
    L. Zhang, R. Ferrero, F. Gandino, M. Rebaudengo
    Proceedings of 11th International Conference on Advances in Mobile Computing & Multimedia (MoMM2013)
    DOI: 10.1145/2536853.2536877
    KEYWORDS: performance evaluation; additive interference model; rfid; unit disk graph
    ABSTRACT: When numerous RFID readers are placed in the same area, they may interfere with each other due to the reader collision problem. In recent years, many studies have been presented to address the reader collision problem. However, there is no consonance on the interference model to use in the analysis of the protocols. The main adopted models are the single interference model, which is simple and fast, but only consid- ers the readers within a threshold distance, and the additive interference model, which sums the interferences of all the concurrent interrogations. Recent studies have shown that the single interference model cannot detect a relevant part of the possible collisions detected by the additive one. This paper analyzes and compares the network performance of an RFID system by applying both the models. Considering two proposed scenarios, the performance of the two models are evaluated and presented

  30. Validation and robustness assessment of an automotive system
    M. Desogus, M. Sonza Reorda, L. Sterpone, V. Avantaggiati, G. Audisio, M. Sabatini
    Proceedings of 8th IEEE International Design & Test Symposium
    KEYWORDS: embedded system; debug; soc; validation; fpga
    ABSTRACT: Due to the growing complexity of automotive systems, including various modules (e.g., microcontrollers, DSPs, memories and IP cores), validation and debug have become increasingly complex, with consequent impact on time-to-market and quality. In this paper we propose a novel flow for hardware and software validation and debug through the use of an FPGA-based emulation platform, which provides a valuable support for these important phases of the development flow. The same emulation platform is also able to support faults injection in the device under validation. Fault injection is intended not only to provide an evaluation of the system fault tolerance, but also to support the debug of the embedded fault tolerance mechanisms. Experimental results on a real industrial case study allow to evaluate the effectiveness and costs of the proposed solution