Publications

  1. A novel simulator for RFID reader-to-reader anti-collision protocols
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo, L. Zhang
    ABSTRACT: Reader-to-reader interference affects the simultaneous activity of the readers in an RFID system: the collisions among the readers penalize the throughput and the reliability of the application. Many reader-to-reader anti-collision protocols have been proposed to address this issue. Their performance is generally evaluated by means of simulations. For this purpose, a generic simulator of wireless networks is exploited in most of the cases. This paper proposes a novel simulator, which is customized to the characteristics of the RFID technology in order to speed up the evaluation of anti-collision protocols. The simulator is based on OMNeT++ and it adds new ad-hoc facilities, such as the implementation of the existing reader-to-reader anti-collision protocols and a modular architecture for rapidly developing and testing new ones

  2. About the functional test of permanent faults in distributed systems
    A. Vaskova, M. Portela-García, C. López-Ongil, E. Sanchez Sanchez, M. Sonza Reorda
    2015 Conference on Design of Circuits and Integrated Systems (DCIS)
    DOI: 10.1109/DCIS.2015.7388571
    ABSTRACT: The effects of permanent faults, arising along working life of digital electronic systems, may impact their reliability and performance. In-field test may help to detect these faults and to prevent serious effects in safety-critical applications. Distributed electronic systems introduce further complexity in this scenario, as the low observability and the lack of maintenance make difficult the detection as well as the identification of failing elements and their repairing. Functional workloads are often used for on-line tests of distributed systems to detect permanent faults. Suitable techniques for test generation and early identification of functionally untestable permanent faults are critical issues that are faced in this work

  3. An Evolutionary Approach for Test Program Compaction
    R. Cantoro, M. Gaudesi, E. Sanchez, P. Schiavone, G. Squillero
    campo non avvalorato
    DOI: 10.1109/LATW.2015.7102406
    KEYWORDS: on-line test; software based self testing; computational intelligence
    ABSTRACT: Abstract— The increasing complexity of electronic components based on microprocessors and their use in safety-critical application - like automotive devices - make reliability a critical aspect. During the life cycle of such products, it is needed to periodically check whether the processor cores are working correctly. In most cases, this task is performed by running short, fast and specialized test programs that satisfies in-field testing requirements. This paper proposes a method that exploits an evolutionary-computation technique for the automatic compaction of these in-field oriented test programs. The aim of the proposed approach is twofold: reduce execution time and memory occupation, while maintaining the fault coverage of the original test program. Experimental results gathered on miniMIPS, a freely available 5-stage pipelined processor core, demonstrate the effectiveness of the proposed technique

  4. An Hybrid Architecture for consolidating mixed criticality applications on multicore systems
    S. Avramenko, S. Esposito, M. Violante, M. Sozzi, M. Traversone, M. Binello, M. Terrone
    Proceedings on the IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2015.7229823

  5. An effective ATPG flow for Gate Delay Faults
    A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    10th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015
    DOI: 10.1109/DTIS.2015.7127350
    ABSTRACT: This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition Delay Faults, a traditional ATPG procedure can be used to determine patterns without any explicit timing information. The latter may account for several iterations, and it is returning the minimum delay that is detected for each delay faults. Effectiveness and feasibility of the proposed ATPG flow have been demonstrated on ISCAS'89 and ITC'99 benchmarks

  6. An innovative parallel fuzzy scheme for low-power consumption in IEEE 802.11 devices
    M. Collotta, S. Tirrito, R. Ferrero, M. Rebaudengo
    DOI: 10.1109/INDIN.2015.7281856
    ABSTRACT: Wireless devices are mainly used in mobile systems because they do not need any physical connection for the communication and the energy supply. Therefore, reducing the power consumption of their batteries is a critical task in order to prolong their lifetime. The main aim of this paper is to dynamically adjust both the sleeping time and the transmission power of mobile devices in an IEEE 802.11 wireless network in order to reduce the power consumption. The algorithm runs on the access point that provides the wireless connection to the devices, so no extra circuitry or computation is required to the devices. The proposal is validated through simulations, which show a battery life 20% higher than other state-of-the-art approaches

  7. Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAS
    B. Du, M. Desogus, L. Sterpone
    2015 11th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2015
    DOI: 10.1109/PRIME.2015.7251378
    KEYWORDS: fpga; radiation experiment; single event effects; sopc; electrical and electronic engineering

  8. Black Holes and Revelations: Using Evolutionary Algorithms to Uncover Vulnerabilities in Disruption-Tolerant NetworksApplications of Evolutionary Computation
    D. Bucur, G. Iacca, G. Squillero, A. Tonda
    Lecture Notes in Computer ScienceApplications of Evolutionary Computation
    DOI: 10.1007/978-3-319-16549-3_3
    ABSTRACT: A challenging aspect in open ad hoc networks is their resilience against malicious agents. This is especially true in complex, urban-scale scenarios where numerous moving agents carry mobile devices that create a peer-to-peer network without authentication. A requirement for the proper functioning of such networks is that all the peers act legitimately, forwarding the needed messages, and concurring to the maintenance of the network connectivity. However, few malicious agents may easily exploit the movement patterns in the network to dramatically reduce its performance. We propose a methodology where an evolutionary algorithm evolves the parameters of different malicious agents, determining their types and mobility patterns in order to minimize the data delivery rate and maximize the latency of communication in the network. As a case study, we consider a fine-grained simulation of a large-scale disruption-tolerant network in the city of Venice. By evolving malicious agents, we uncover situations where even a single attacker can hamper the network performance, and we correlate the performance decay to the number of malicious agents

  9. Chromatic Selection - An Oversimplified Approach to Multi-objective OptimizationApplications of Evolutionary Computation
    G. Squillero
    Lecture Notes in Computer ScienceApplications of Evolutionary Computation
    DOI: 10.1007/978-3-319-16549-3_55
    ABSTRACT: This short paper introduces the chromatic selection, a simple technique implementable with few tens of lines of code, that enable handling multi-value fitness functions with a single-objective evolutionary optimizer. The chromatic selection is problem independent, requires no parameter tuning, and can be used as a drop-in replacement for both parent and survival selections. The resulting tool will not be a full-fledged multi-objective optimizer, lacking the ability to manage Pareto fronts, but it will efficiently seek a single, reasonable, compromise solution. In several practical problems, the time saved, both in computation and development, could represent a substantial advantage

  10. Design Space Exploration and Optimization of a Hybrid Fault-Tolerant Architecture
    Wali,I., A. Virazel, A. Bosio, P. Girard, M. Sonza Reorda
    21st IEEE International On-Line Testing Symposium
    KEYWORDS: fault tolerance, redundancy, transient and permanent faults, power consumption
    ABSTRACT: Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency. Thus, in this paper we present design space exploration and optimization of the Hybrid Fault-Tolerant Architecture. The study involves application of four design variants to some ITC benchmark circuits as case study. Experimental results compare the initial and optimized designs and show that the proposed optimizations offer around 65% reduction in terms of area, about 55% power saving and 87% less performance overhead as compared to the initial design without any penalty of the fault tolerance capability

  11. Evaluation of error effects on a biomedical system
    B. Enea, V. Massimo, H. Hakob
    Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2015)
    DOI: 10.1109/EWDTS.2015.7493164
    KEYWORDS: reliability, safety-critical, model-based, fault injection, biomedical system modeling
    ABSTRACT: The evaluation of the reliability of a safety-critical system in the design phase is crucial as it allows to strengthen the weaknesses of products prior to the production phase, when the countermeasures could be expensive and/or ineffective. In some domains, it is common to adopt a design flow exploiting a high-level description of the system behavior and architecture from which the software, and eventually the hardware, can be automatically generated. In this paper we applied the concept to the design of a pacemaker. Starting from a high-level model, by exploiting automatic code generation, we derived the C code implementing the pacemaker functionality, then we evaluated its robustness against transient errors that may affect the computing resources used to execute the generated code. When compared to previous works that focused on reliability analysis of the pacemaker high-level model, only, this paper highlights the importance of considering both the high-level model, and the corresponding implementation in C code to allows for accurate and comprehensive reliability analysis

  12. Experimental Investigation on the Interference between UHF RFID and GSM
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    ABSTRACT: Radio Frequency Identification (RFID) is a widely employed technology for automatic identification. However, it is affected by some interference issues. This paper is focused on the interference between Ultra high frequency (UHF) RFID systems and devices that communicate according to the Global System for Mobile Communications (GSM) standard. Since the GSM and the UHF RFID frequency bands are close, the mobile phones communication can affect the efficiency of RFID systems. In this paper, an experimental analysis on the interference between GSM and UHF RFID is presented. The results of the experimentation highlight the negative effects of the use of GSM devices in the proximity of operating UHF RFID systems. Moreover, the main elements that should be taken into account during the design of an RFID system that works in the same area with GSM devices are identified

  13. Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs
    R. Cantoro, M. Gaudesi, E. Sanchez, G. Squillero
    Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2739482.2764673
    KEYWORDS: software-based self-test, testing, evolutionary computation
    ABSTRACT: It is well-known that faults affecting an electronic device may compromise its correct functionality, and industries have to check that their devices are fault-free before selling them. In case of a processor core, this task may be accomplished by running specially written "test" programs. In industrial embedded applications, however, shrinking such programs is strictly required. The hard problems of generating and code-optimizing test programs are tackled in this paper by exploiting an evolutionary approach

  14. Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing
    A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
    KEYWORDS: power aware test, functional and structural test, microprocessor test, atpg
    ABSTRACT: High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget

  15. In-field test of safety-critical systems: is functional test a feasible solution?
    M. Sonza Reorda
    2015 16th IEEE Latin-American Test Symposium (LATS)
    DOI: 10.1109/LATW.2015.7102528
    ABSTRACT: The growing usage of electronic systems in safety- and mission-critical applications, together with the increased susceptibility of electronic devices to faults arising during the operational phase mandate for the availability of effective solutions able to face the effects of these faults. When the target system includes a processor, one possible solution is based on running suitable test programs able to detect the occurrence of faults. This solution provides several advantages (e.g., in terms of flexibility, IP protection, and defect coverage), although it is limited by the cost for developing the test programs. This paper overviews the state of the art in the area, and discusses the trends in the area

  16. Malware Obfuscation through Evolutionary Packers
    M. Gaudesi, A. Marcelli, E. Sanchez, G. Squillero, A. Tonda
    Proceedings of the Companion Publication of the 2015 Annual Conference on Genetic and Evolutionary Computation
    DOI: 10.1145/2739482.2764940
    KEYWORDS: evolutionary computation, virus
    ABSTRACT: A malicious botnet is a collection of compromised hosts coordinated by an external entity. The malicious software, or malware, that infect the systems are its basic units and they are responsible for its global behavior. Anti Virus software and Intrusion Detection Systems detect botnets by analyzing network and files, looking for signature and known behavioral patterns. Thus, the malware hiding capability is a crucial aspect. This paper describes a new obfuscation mechanism based on evolutionary algorithms: an evolutionary core is embedded in the malware to generate a different, optimized hiding strategy for every single infection. Such always-changing, hard-to-detect malware can be used by security industries to stress the analysis methodologies and to test the ability to react to malware mutations. This research is the first step in a more ambitious research project, where a whole botnet, composed of different malware and Anti Virus software, is analyzed as a prey-predator ecosystem

  17. Observability solutions for in-field functional test of processor-based systems
    J. Perez Acle, R. Cantoro, A. Hailemichael, E. Sanchez, M. Sonza Reorda
    KEYWORDS: microprocessor testing, software-based self-test
    ABSTRACT: The growing usage of electronic systems in safety-critical applications requires effective solutions to early identify possible faults affecting the hardware while it is in the operational phase. A possible approach leverages functional programs to be run by the CPU typically existing in such systems. These programs must exercise the different parts of the system, and produce a behavior different than the normal one in case of faults. However, their effectiveness depends on the adopted observation mechanism, which is deeply affected by the constraints imposed by the in-field application environment. This paper first describes different mechanisms for supporting the observation of possible fault effects; then, it reports and discusses the results of an experimental analysis performed on a multicore system, based on a representative pipelined processor. The gathered results allow to quantitatively evaluate the drop in fault coverage coming from the adoption of the different observation solutions with respect to the ideal case, and thus to better evaluate the advantages/disadvantages they provide

  18. On Test Program Compaction
    M. Gaudesi, M. Sonza Reorda, I. Pomeranz
    campo non avvalorato
    DOI: 10.1109/ETS.2015.7138771
    KEYWORDS: test program generation
    ABSTRACT: While compaction of binary test sequences for generic sequential circuits has been widely explore, the compaction of test programs for processor based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This paper is among the first to propose algorithms able to automatically compact an existing test program. The proposed solution is based on instruction removal and restoration, which is shown to significantly reduce the computational cost compared with instruction removal alone. Experimental results are reported, showing the compaction capabilities and computational costs of the proposed algorithms

  19. On gait recognition with smartphone accelerometer
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo, A. Velasco, I. Benkhelifa
    DOI: 10.1109/MECO.2015.7181946
    KEYWORDS: gait analysis; biometric authentication; mobile phone; 3-axis accelerometer
    ABSTRACT: Besides revealing useful information, like gender, age, existing impairments, the gait of every person is acknowledged to be so distinctive to allow the personal identification and it is regarded as a valid biometric authentication, similarly to fingerprinting and face recognition. Although the first analyses on the gait were conducted in laboratories with dedicated equipment, portable sensors have been exploited as they become available thanks to the technology miniaturization. Aiming at an even more unobtrusive analysis, recent proposals rely on the data acquired from the 3-axis accelerometer embedded in most of the smartphones commercially available on the market. Nevertheless the analysis must be tailored to the lower-grade accelerometer and the limited computational capability of the smartphone. This paper identifies the guidelines that the state-of-the-art research proposes for the gait recognition through a smartphone and discusses the procedures that are found as more appropriate

  20. On the Automatic Generation of SBST Test Programs for In-Field Test
    A. Riefert, R. Cantoro, M. Sauer, M. Sonza Reorda, B. Becker
    Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
    DOI: 10.7873/DATE.2015.0271
    KEYWORDS: atpg; software based self testing; test programs
    ABSTRACT: Software-based self-test (SBST) techniques are used to test processors against permanent faults introduced by the manufacturing process (often as a complementary approach with respect to DfT) or to perform in-field test in safety-critical applications. A major obstacle to their adoption is the high cost for developing effective test programs, since there is still a lack of suitable EDA algorithms and tools able to automatically generate SBST test programs. An efficient ATPG algorithm can serve as the foundation for the automatic generation of SBST test programs. In this work we first highlight the additional constraints characterizing SBST test programs wrt functional ones, with special emphasis on their usage for in-field test; then, we describe an ATPG framework targeting stuck-at faults based on Bounded Model Checking. The framework allows the user to exibly specify the requirements of SBST test programs in the considered scenario. Finally, we demonstrate how a set of properly chosen requirements can be used to generate test programs matching these constraints. In our experiments we evaluate the framework with the miniMIPS microprocessor. The results show that the proposed method is the first able to automatically generate SBST test programs whose fault efficiency is superior to those produced with state-of-the-art manual approaches

  21. On the Design of Highly Reliable System-on-Chip using Dynamically Reconfigurable FPGAs
    C. David Merodio, B. Du, L. Sterpone, L. Venditti
    Titolo non avvalorato
    DOI: 10.1109/ReCoSoC.2015.7238082
    KEYWORDS: sram chips field programmable gate arrays logic design radiation hardening (electronics) system-on-chip
    ABSTRACT: Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude

  22. On the Functional Test of the Cache Coherency Logic in Multi-core Systems
    J. Perez Acle, R. Cantoro, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/LASCAS.2015.7250453
    KEYWORDS: futional testing; multicore testng; cache cncy logic; sbst
    ABSTRACT: Multi-core systems are becoming particularly common, due to the high performance they can deliver. Higher, their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach; this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. We validated our method on a LEON3 multicore system

  23. On the Maximization of the Sustained Switching Activity in a Processor
    R. Cantoro, M. Sonza Reorda, A. Rohani, H. Kerkhoff
    21st IEEE International On-Line Testing Symposium
    KEYWORDS: switching activity, burn-in, aging
    ABSTRACT: Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor

  24. On the Testability of IEEE 1687 Networks
    R. Cantoro, M. Montazeri, M. Sonza Reorda, F. Ghani Zadegan, E. Larsson
    DOI: 10.1109/ATS.2015.7447934
    KEYWORDS: ijtag, ieee 1687, testing, scan chains
    ABSTRACT: Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach

  25. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors
    H. Ghasemzadeh, P. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M. Reorda
    Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
    DOI: 10.1109/ISVLSI.2015.13
    KEYWORDS: controllable-polarity transistors; fault model; fault-tolerant adder; hardware and architecture; control and systems engineering; electrical and electronic engineering

  26. On the design of distributed air quality monitoring systems
    A. Velasco, R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    KEYWORDS: air pollutants; wireless sensor network; pervasive monitoring
    ABSTRACT: Nowadays, the air quality is considered a key point, and its monitoring is not only suggested but it is even required in many countries. Since traditional standard monitors for air quality are very expensive, the use of a low-cost distributed network of sensors represents a valid complementary approach. This paper discusses the benefits of a distributed approach and analyzes the main elements that should be taken into account during the design of a distributed system for the air quality monitoring. This paper aims at representing a valuable aid for researchers and practitioners interested in the topic

  27. Operator Selection using Improved Dynamic Multi-Armed Bandit
    J. Belluz, M. Gaudesi, G. Squillero, A. Tonda
    GECCO '15 Proceedings of the 2015 on Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2739480.2754712
    ABSTRACT: Evolutionary algorithms greatly benefit from an optimal application of the different genetic operators during the optimization process: thus, it is not surprising that several research lines in literature deal with the self-adapting of activation probabilities for operators. The current state of the art revolves around the use of the Multi-Armed Bandit (MAB) and Dynamic Multi-Armed bandit (D-MAB) paradigms, that modify the selection mechanism based on the rewards of the different operators. Such methodologies, however, update the probabilities after each operator's application, creating possible issues with positive feedbacks and impairing parallel evaluations, one of the strongest advantages of evolutionary computation in an industrial perspective. Moreover, D-MAB techniques often rely upon measurements of population diversity, that might not be applicable to all real-world scenarios. In this paper, we propose a generalization of the D-MAB approach, paired with a simple mechanism for operator management, that aims at removing several limitations of other D-MAB strategies, allowing for parallel evaluations and self-adaptive parameter tuning. Experimental results show that the approach is particularly effective with frameworks containing many different operators, even when some of them are ill-suited for the problem at hand, or are sporadically failing, as it commonly happens in the real world

  28. Permanent Fault Detection and Diagnosis in the Lightweight Dual Modular Redundancy Architecture
    R. Ferreira, E. Sanchez, J. Da Rolt, G. Nazar, A. Moreira, L. Carro, M. Sonza Reorda
    KEYWORDS: modular redundancy; error detection; reliable architecture

  29. Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG
    N. Palermo, V. Tihhomirov, T. Copetti, M. Jenihhin, J. Raik, S. Kostin, M. Gaudesi, G. Squillero, M. Reorda, F. Vargas, L. Poehls
    2015 16th Latin-American Test Symposium, LATS 2015
    DOI: 10.1109/LATW.2015.7102405
    KEYWORDS: aging; critical path identification; evolutionary computation; hardware rejuvenation; logic circuit; microgp; nbti; zamiacad; hardware and architecture; electrical and electronic engineering; computer science applications1707 computer vision and pattern recognition; software; control and systems engineering; safety, risk, reliability and quality
    ABSTRACT: One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTI-critical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design

  30. SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs
    B. L. Sterpone
    Applied Reconfigurable Computing
    DOI: 10.1007/978-3-319-16214-0_11
    KEYWORDS: fault tolerance; reconfigurable; radiation effects; test; fpga; place and route

  31. SW-Based Transparent In-Field Memory Testing
    P. Bernardi, L. Ciganda, M. Sonza Reorda, S. Hamdioui
    16th IEEE Latin American Test Symposium
    ABSTRACT: With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on, during idle times) is becoming mandatory. Due to the strict constraints of in-field test, transparent BIST is extremely attractive, since it allows to minimize test invasiveness. This paper presents a cheap, high quality and practical SW-based transparent in-field test approach for memories within a system. Instead of using hardware BIST, the proposed scheme re-uses the CPU to perform in-field testing for all memories within the system. All quality metrics of the proposed solution (such as defect coverage, test time and code size) are analyzed. Case studies using the ARM instruction set architecture are provided to demonstrate the applicability of the solution. With the proposed approach no hardware BIST is necessary and speed-related faults are tackled, whereas results show the test time complexity of the SW-based transparent tests is the same as the one of the standard hardware BIST test. Moreover, data previously present in the memory is not corrupted with, in average, only a 30% increase in test program size with respect to non-transparent SW-based test

  32. Scan-Chain Intra-Cell Defects Grading
    A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    10th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
    DOI: 10.1109/DTIS.2015.7127349
    KEYWORDS: intra-cell defect; test; fault simulation; scan-chain testing
    ABSTRACT: With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell defect coverage affecting scan flip-flops. The experimental results show that a meaningful test solution has to be developed to improve the overall defect coverage for the scan chain testing

  33. Software-based self-test techniques of computational modules in dual issue embedded processors
    P. Bernardi, C. Bovi, R. Cantoro, S. De Luca, R. Meregalli, D. Piumatti, E. Sanchez, A. Sansonetti
    DOI: 10.1109/ETS.2015.7138730
    KEYWORDS: embedded systems; software-based self-test; sbst; system-on-chip; microprocessor testing; embedded systems; software-based self-test; sbst; system-on-chip; microprocessor testing
    ABSTRACT: Self-Test strategies for testing embedded processors are increasingly diffused. In this paper, we describe a set of self-test techniques tackling dual issue embedded processors. The paper details how to produce test programs suitable to detect stuck-at faults in computational modules belonging to dual issue processors. The proposed technique is aimed at extending single issue test programs; results are illustrated for a 32-bit processor included in an automotive System-on-Chip manufactured by STMicroelectronics and implementing a dual issue strategy with static dispatch of instructions.

  34. The EcoThermo project: key and innovative aspects
    F. Bari, D. Mereu, C. Damarco, C. Greco, S. Malan, G. Marchetto, S. Roa Tirado, R. Tisseur, M. Violante, G. Zangari, S. Caruso, M. Masoero, F. Saba
    Energy Procedia
    DOI: 10.1016/j.egypro.2015.11.697
    KEYWORDS: thermal comfort; energy efficiency; energy control; smart buildings; eu project
    ABSTRACT: In this paper we present the most innovative aspects of the EC-FP7 EcoThermo project. The main aim of the project consists on innovating the technique of heat cost allocation in buildings with a centralized heating system, overcoming the heat cost allocator drawbacks for reliability, measurement reproducibility and traceability and contexts of applications. Given the complexity of the project, we will focus on its main aspects, such as the use of a virtual sensor to estimate the radiators heating power, the design of electronic valves fitted out with an energy harvesting system and the original wireless communication protocol

  35. Towards automatic StarCraft strategy generation using genetic programming
    P. Garcia-Sanchez, A. Tonda, A. Mora, G. Squillero, J. Merelo
    Proceedings 2015 IEEE Conference on Computational Intelligence and Games
    DOI: 10.1109/CIG.2015.7317940
    KEYWORDS: starcraft; evolutionary computation; games; real-time strategy
    ABSTRACT: Among Real-Time Strategy games few titles have enjoyed the continued success of StarCraft. Many research lines aimed at developing Artificial Intelligences, or "bots", capable of challenging human players, use StarCraft as a platform. Several characteristics make this game particularly appealing for researchers, such as: asymmetric balanced factions, considerable complexity of the technology trees, large number of units with unique features, and potential for optimization both at the strategical and tactical level. In literature, various works exploit evolutionary computation to optimize particular aspects of the game, from squad formation to map exploration; but so far, no evolutionary approach has been applied to the development of a complete strategy from scratch. In this paper, we present the preliminary results of StarCraftGP, a framework able to evolve a complete strategy for StarCraft, from the building plan, to the composition of squads, up to the set of rules that define the bot's behavior during the game. The proposed approach generates strategies as C++ classes, that are then compiled and executed inside the OpprimoBot open-source framework. In a first set of runs, we demonstrate that StarCraftGP ultimately generates a competitive strategy for a Zerg bot, able to defeat several human-designed bots