Articles

  1. A Low-Cost Solution for Deploying Processor Cores in Harsh Environments
    Sonza Reorda M., Violante M, Meinhardt C., Reis R.
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2011, pp. 2617-2626

  2. A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test
    Ciganda L., Bernardi P., Sonza Reorda M., Barbieri D., Bonaria L., Losco R., Marcigot L., Straiotto M.
    JOURNAL OF ELECTRONIC TESTING, 2011, pp. 389-402

  3. An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-based FPGAs
    L. Sterpone, N. Battezzati, F. Lima Kastensmidt, R. Chipana
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2011, pp. 2333-2340

  4. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    Battezzati N., Margaglia F., Violante M., Decuzzi F., Merodio Codinachs D., Bancelin B.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2011, pp. 987-992

  5. Artificial evolution in computer aided design: from the optimization of parameters to the creation of assembly programs
    G. Squillero
    COMPUTING, 2011, pp. 103-120

  6. Coping With the Obsolescence of Safety - or Mission-Critical Embedded Systems Using FPGAs
    Guzman-Miranda H., Sterpone L., Violante M., Aguirre M., Gutierrez-Rizo M.
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2011, pp. 814-821

  7. Covariance Matrix Adaptation Evolutionary Strategy for Drift Correction of Electronic Nose Data
    Di Carlo S., Falasconi M., Sanchez E., Sberveglieri G., Scionti A., Squillero G., Tonda A.
    AIP CONFERENCE PROCEEDINGS, 2011, pp. 25-26

  8. Functional Verification of DMA Controllers
    Grosso M., Perez H.W.J., Ravotto D., Sanchez E., Sonza Reorda M., Tonda A., Velasco Medina J.
    JOURNAL OF ELECTRONIC TESTING, 2011, pp. 505-516

  9. Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation
    Di Carlo S., Falasconi M., Sanchez E.., Scionti A., Squillero G., Tonda A.
    PATTERN RECOGNITION LETTERS, 2011, pp. 1594-1603

  10. Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs
    Sterpone L., Violante M., Panariti A., Bocquillo A., Miller F., Buard N., Manuzzato A., Gerardin S., Paccagnella A.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2011, pp. 2325-2332

  11. Probabilistic DCS: An RFID reader-to-reader anti-collision protocol
    F. Gandino; R. Ferrero, B. Montrucchio; M. Rebaudengo
    JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, 2011, pp. 821-832

  12. A Framework for Automated Detection of Power-Related Software Errors in Industrial Verification Processes
    Gandini S. , Ruzzarin W. , Sanchez E. , Squillero G., Tonda A.
    JOURNAL OF ELECTRONIC TESTING, 2010, pp. 689-697

  13. A Hybrid Approach for Detection and Correction of Transient Faults in SoCs
    Bernardi P., Grosso M., Bolzani Poehls L., Sonza Reorda M.
    IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2010, pp. 439-445

  14. A new Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
    Sterpone L.
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2010, pp. 7.1-7.21

  15. Analysis of SET propagation in Flash-based FPGAs by means of electrical pulse injection
    Sterpone L., Battezzati N., Ferlet-Cavrois V.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, pp. 1820-1826

  16. Boosting Software Fault Injection for Dependability Analysis of Real-Time Embedded Applications
    Cabodi G; Murciano M.; Violante M
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2010, pp. 24:1-24:32

  17. Design Validation of Multithreaded Processors using Threads Evolution
    D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
    JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, pp. 67-77

  18. Evaluating the Impact of DFM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core
    Appello D.; Grosso M.; Loparco D.; Melchiori F.; Paccagnella A.; Rech P.; Sonza Reorda M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, pp. 2098-2105

  19. Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug
    Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M
    IET COMPUTERS & DIGITAL TECHNIQUES, 2010, pp. 104-113

  20. Microprocessor Software-Based Self-Testing
    Psarakis M., Gizopoulos D., Sanchez E., Sonza Reorda M.
    IEEE DESIGN & TEST OF COMPUTERS, 2010, pp. 4-19

  21. Microvesicles Derived from Adult Human Bone Marrow and Tissue Specific Mesenchymal Stem Cells Shuttle Selected Pattern of miRNAs
    Collino F., Deregibus M.C., Bruno S., Sterpone L., Aghemo G., Viltono L., Tetta C., Camussi G.
    PLOS ONE, 2010, pp. 1-15

  22. Tampering in RFID: A Survey on Risks and Defenses
    F. Gandino; B. Montrucchio; M. Rebaudengo
    JOURNAL ON SPECIAL TOPICS IN MOBILE NETWORKS AND APPLICATIONS, 2010, pp. 502-516

  23. A Novel Dual Core Architecture for the Analysis of DNA Microarray Images
    Sterpone L.
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2009, pp. 2653-2662

  24. Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs
    Appello D; Bernardi P; Grosso M.; Sanchez E; Sonza Reorda M
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, pp. 1654-1659

  25. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    Battezzati N.; S. Gerardin; A. Manuzzato; D. Merodio; A. Paccagnella; C. Poivey; L. Sterpone; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, pp. 3534-3541

  26. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
    Abate F.; L. Sterpone; C.A. Lisboa; L. Carro; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, pp. 1992-2000

  27. On Improving Automation by Integrating RFID in the Traceability Management of the Agri-Food Sector
    F. Gandino; B. Montrucchio; M. Rebaudengo; E.R. Sanchez
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2009, pp. 2357-2365

  28. Opportunity and Constraints for Wide Adoption of RFID in Agri-Food
    F. Gandino; E.R. Sanchez; B. Montrucchio; M. Rebaudengo
    INTERNATIONAL JOURNAL OF ADVANCED PERVASIVE AND UBIQUITOUS COMPUTING, 2009, pp. 49-67

  29. Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip
    Apostolakis A; Gizopoulos D; Psarakis M; Ravotto D.; Sonza Reorda M
    IEEE DESIGN & TEST OF COMPUTERS, 2009, pp. 52-63

  30. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate; Sterpone L.; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, pp. 2063-2069

  31. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    Sterpone L; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, pp. 2019-2027

  32. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi; E. Sanchez; M. Schillaci; G. Squillero; Sonza Reorda M.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, pp. 570-574

  33. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato; S. Gerardin; A. Paccagnella; Sterpone L.; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, pp. 1968-1973

  34. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    Eduardo Luis Rhod; Carlos Arthur Lang Lisbôa; Luigi Carro; Sonza Reorda M.; Massimo Violante
    JOURNAL OF ELECTRONIC TESTING, 2008, pp. 45-56

  35. Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-based FPGAs
    N. Battezzati; Sterpone L.; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, pp. 3381-3387

  36. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    Alderighi M; Casini F; D'Angelo S; Mancini M; Pastore S; Sterpone L.; Violante M
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, pp. 2267-2273

  37. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini; A. Miele; M. Rebaudengo; F. Salice; Sterpone L.; M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2008, pp. 35-44

  38. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    Sterpone L; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, pp. 965-970

  39. A System-layer Infrastructure for SoC Diagnosis
    Bernardi P; Grosso M; Rebaudengo M.; Sonza Reorda M
    JOURNAL OF ELECTRONIC TESTING, 2007, pp. 389-404

  40. A new approach to estimate the effect of single event transients in complex circuits
    Aguirre M. A; Baena V; Tombs J; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, pp. 1018-1024

  41. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    Violante M.; Sterpone L; Manuzzato A; Gerardin S; Rech P; Bagatin M; Paccagnella A; Andreani C; Gorini G; Pietropaolo A; Cardarilli G; Pontarelli S; Frost C
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, pp. 1184-1189

  42. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    Sonza Reorda M; Sterpone L; Violante M.; Lima Kastensmidt F; Carro L
    JOURNAL OF ELECTRONIC TESTING, 2007, pp. 47-54

  43. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    Sterpone L; Violante M.; Harboe Sorensen R; Merodio D; Sturesson F; Weigand R; Mattsson S
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, pp. 2576-2583

  44. A new hybrid fault detection technique for systems-on-a-chip
    Bernardi P.; Veiras Bolzani Lm.; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante
    IEEE TRANSACTIONS ON COMPUTERS, 2006, pp. 185-198

  45. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone; Violante M.
    IEEE TRANSACTIONS ON COMPUTERS, 2006, pp. 732-744

  46. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone; Violante M.; S. Rezgui
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, pp. 2054-2059

  47. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez; Sonza Reorda M.; M. Violante
    IEEE DESIGN & TEST OF COMPUTERS, 2006, pp. 38-45

  48. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
    Sanchez E; Sonza Reorda M; Squillero G.
    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2006, pp. 93-109

  49. HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC
    Bernardi P.; L. Sterpone; M. Violante; M. Portela-Garcia
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, pp. 3550-3557

  50. Hardening FPGA-based systems against SEUs: A new design methodology
    Sterpone L; Violante M.
    JOURNAL OF COMPUTERS, 2006, pp. 22-30

  51. System-in-package testing: problems and solutions
    Appello D; Bernardi P; Grosso M.; Sonza Reorda M
    IEEE DESIGN & TEST OF COMPUTERS, 2006, pp. 203-211

  52. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, pp. 2217-2223

  53. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, pp. 1545-1549

  54. Automatic Test Generation for Verifying Microprocessors
    Corno F.; E. Sanchez; M. Sonza Reorda; G. Squillero
    IEEE POTENTIALS, 2005, pp. 34-37

  55. Evolving assembly programs: how games help microprocessor validation
    Corno F; Sanchez E; Squillero G.
    IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2005, pp. 695-706

  56. MicroGP - An Evolutionary Assembly Program Generator
    Squillero G.
    GENETIC PROGRAMMING AND EVOLVABLE MACHINES, 2005, pp. 247-263

  57. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello; A. Fudoli; V. Tancorre; Bernardi P.; F. Corno; M. Rebaudengo; M. Sonza Reorda
    JOURNAL OF ELECTRONIC TESTING, 2004, pp. 79-87

  58. A new approach to software-implemented fault tolerance
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2004, pp. 433-437

  59. Automatic Test Program Generation: a Case Study
    Corno F.; Sanchez E.; Sonza Reorda M.; Squillero G.
    IEEE DESIGN & TEST OF COMPUTERS, 2004, pp. 102-109

  60. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno; E. Sanchez; Sonza Reorda M.; G. Squillero
    JOURNAL OF ELECTRONIC TESTING, 2004, pp. 269-278

  61. Efficient analysis of single event transients
    M. Sonza Reorda; Violante M.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2004, pp. 239-246

  62. Evolutionary Simulation-Based Validation
    Corno F.; M. Sonza Reorda; G. Squillero
    INTERNATIONAL JOURNAL ON ARTIFICIAL INTELLIGENCE TOOLS, 2004, pp. 897-916

  63. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante; L. Sterpone; M. Ceschia; D. Bortolato; P. Bernardi; Sonza Reorda M.; A. Paccagnella
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2004, pp. 3354-3359

  64. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo; M. Sonza Reorda; Violante M.
    JOURNAL OF ELECTRONIC TESTING, 2003, pp. 577-584

  65. Accurate single-event-transient analysis via zero-delay logic simulation
    Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003, pp. 2113-2118

  66. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia; M. Violante; M. Sonza Reorda; A. Paccagnella; P. Bernardi; Rebaudengo M.; D. Bortolato; M. Bellato; P. Zambolin; A. Candelori
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003, pp. 2088-2094

  67. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure; R. Velazco; M. Rebaudengo; M. Sonza Reorda; Violante M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003, pp. 2101-2106

  68. New Techniques for efficiently assessing reliability of SOCs
    P. Civera; L. Macchiarulo; M. Rebaudengo; Sonza Reorda M.; M. Violante
    MICROELECTRONICS JOURNAL, 2003, pp. 53-61

  69. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2002, pp. 261-271

  70. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    Rebaudengo M.; M. Sonza Reorda; M. Violante; B. Nicolescu; R. Velazco
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2002, pp. 1491-1495

  71. Initializability Analysis of Synchronous Sequential Circuits
    Corno F.; P. Prinetto; M. Rebaudengo; M. Sonza Reorda; G. Squillero
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2002, pp. 249-264

  72. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2001, pp. 2210-2216

  73. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet; B. Nicolescu; R. Velazco; Rebaudengo M.; M. Sonza Reorda; M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2000, pp. 2231-2236

  74. RT-level ITC'99 benchmarks and first ATPG results
    Corno F.; M. Sonza Reorda; G. Squillero
    IEEE DESIGN & TEST OF COMPUTERS, 2000, pp. 44-53

  75. Fault Injection for Embedded Microprocessor-based Systems
    Benso A.; Rebaudengo M.; Sonza Reorda M.
    JOURNAL OF UNIVERSAL COMPUTER SCIENCE, 1999, pp. 693-712

  76. SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
    F. Corno; P. Prinetto; M. Sonza Reorda; Violante M.; U. Glaeser; H.T. Vierhaus
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, pp. 191-202

  77. EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards
    Benso A; Prinetto P; Rebaudengo M.; Sonza Reorda M
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 1998, pp. 626-634

  78. Integrating On-Line and Off-Line Testing of a Switching Memory in a Telecommunication System
    S. Barbagallo; F. Corno; D. Medina; P. Prinetto; Sonza Reorda M.
    IEEE DESIGN & TEST OF COMPUTERS, 1998

  79. The General Product Machine: a New Model for Symbolic FSM Traversal
    Cabodi G.; Camurati P.; Corno F.; Prinetto P.; Sonza Reorda M.
    FORMAL METHODS IN SYSTEM DESIGN, 1998, pp. 267-289

  80. GALLO: a Genetic Algorithm for Floorplan Area Optimization
    Rebaudengo M.; Sonza Reorda M
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, pp. 943-951

  81. GATTO: A Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    Corno F.; Prinetto P; Rebaudengo M; Sonza Reorda M
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, pp. 991-1000

  82. Role of fault injection techniques in system dependability analysis
    Benso A; Corno F; Prinetto P; Rebaudengo M.; Sonza Reorda M
    AEI AUTOMAZIONE ENERGIA INFORMAZIONE, 1996, pp. 63-69

  83. Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions
    F. Corno; P. Prinetto; Sonza Reorda M.
    IEEE DESIGN & TEST OF COMPUTERS, 1996, pp. 50-60