CAD

Papers on ATPG

  1. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vo. 27, No. 3, pp. 570-574, March 2008
  2. System-level Test and Validation of Hardware/Software Systems
    M. Sonza Reorda, Z. Peng, M. Violante
    Series: Springer Series in Advanced Microelectronics, Vol. 17, Springer, London (UK), ISBN 1-85233-899-7
  3. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  4. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  5. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  6. High-level test generation for hardware testing and software validation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2003: IEEE International Workshop on High Level Design Validation and Test, 2003, pp- 143-148
  7. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  8. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  9. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94
    Outstanding Paper Award
  10. High-Level and Hierarchical Test Sequence Generation
    G. Jervan, Z. Peng, O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2002: IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 169-174
  11. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  12. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  13. Behavioral-level fault models comparison: an experimental approach
    O. Goloubeva, M. Sonza Reorda, M. Violante
    ICAM2002, Computer-aided Technologies in Applied Mathematics, September 2002, Tomsk, Russia
  14. Experimental analysis of fault models for behavioral-level test generation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DDECS2002: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2002, pp. 416-419
  15. Behavioral-level test vector generation: fault model selection and preliminary test generation results
    O. Goloubeva, M. Sonza Reorda, M. Violante
    Design of Circuits and Integrated Systems, 2002
  16. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  17. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  18. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  19. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  20. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  21. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  22. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  23. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  24. High-level ATPG: a real topic or an academic amusement?
    M. Sonza Reorda
    IEEE International Test Conference, Atlantic City (USA), September 1999, Poster Session, pp. 1118
  25. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  26. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  27. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  28. RT-level TPG Exploiting High-Level Synthesis Information
    S. Chiusano, F. Corno, P. Prinetto
    17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999
  29. SymFony: a Hybrid Topological-Symbolic ATPG exploiting RT-level Information
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante, U. Glaeser, H. T. Vierhaus
    IEEE Transactions on Computer-Aided Design, February 1999, Vol. 18, No. 2, pp. 191-202
  30. Exploiting Behavioral Information in Gate-Level ATPG
    S. Chiusano, F. Corno, P. Prinetto
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, December 1998
  31. A Test Pattern Generation Algorithm Exploiting Behavioral Information
    S. Chiusano, F. Corno, P. Prinetto
    ATS98, Asian Test Symposium, Singapore, December 1998
  32. Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
    F. Corno, J. H. Patel, E. M. Rudnick, M. Sonza Reorda, R. Vietti
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998
  33. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Sonza Reorda, M. Rebaudengo
    Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, SPIE 1998 Annual Meeting
    Invited paper
  34. A Test Pattern Generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  35. Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
    E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  36. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  37. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  38. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
  39. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386
  40. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
  41. SAARA: a Simulated Annealing Algorithm for Test Pattern Generation for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    SAC97: 12th Annual ACM Symposium on Applied Computing, San Jose, CA (USA), February 1997, pp. 228-232
  42. Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Fourth International Conference on Parallel Problem Solving from Nature, Berlin (Germany), September 1996
  43. Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1996
  44. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Confernce, Washington (USA), October 1996
  45. A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Brussels (Belgium), April 1996
  46. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    IEEE Design & Test Conference, Paris (F), March 1996
  47. GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 943-951
  48. Uso di Tecniche Evolutive per la Risoluzione di problemi di CAD Elettronico
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Processori Dedicati, a cura di Lanfranco Lopriore, Fabrizio Luccio e Maria Marinaro, Collana CNR/Progetto Finalizzato "Sistemi Informatici e Calcolo Parallelo" diretta da Bruno Fadini, Franco Angeli Editore
  49. Improving Topological ATPG with Symbolic Techniques
    F. Corno, U. Glaeser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, H. T. Vierhaus
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  50. A Portable ATPG tool for Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  51. A PVM tool for Automatic Test Generation on Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  52. GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE International Conference on Tools with Artificial Intelligence, New Orleans (USA), November 1994
  53. An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  54. Exploiting a Workstation Network for Automatic Generation of Test Patterns for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A. R. Meo, E. Veiluva
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  55. An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 4, January 1993, pp. 11-17
  56. System-Level Fault Modeling and Test Pattern Generation with Process Algebras
    P. Camurati, F. Corno, P. Prinetto
    ETC93: IEEE European Test Conference, Rotterdam (NL), April 1993, pp. 47-56
  57. Tecniche di diagnosi per circuiti sequenziali
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume II, pp. 737-748
  58. Improved techniques for multiple stuck-at-fault analysis using single stuck-at fault test
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ISCAS 92: IEEE International Symposium on Circuits and Systems, San Diego, CA (USA), Maggio 1992, pp. 383-386
  59. Sequential circuit diagnosis based on formal verification techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC92: IEEE International Test Conference, Baltimore, MD (USA), September 1992, pp. 187-196
  60. Cross-fertilizing FSM verification techniques and sequential diagnosis
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC92: IEEE European Design Automation Conference, Hamburg (Germany), September 1992, pp. 306-311
  61. A simulation-based approach to test pattern generation for synchronous circuits
    P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS92: 10th IEEE VLSI Test Symposium, Atlantic City, NJ (USA), April 1992, pp. 263-267