CAD

Papers on Approximate Methods

  1. Artificial evolution in computer aided design: from the optimization of parameters to the creation of assembly programs
    G. Squillero
    Computing, Special Issue on Bio-inspired Computing, Volume 93, Numbers 2-4, 103-120
  2. Automatic generation of software-based functional failing test for speed debug and on-silicon timing verification
    E. Sanchez, G. Squillero, A. Tonda
    MTV11: International Workshop on Microprocessor Test and Verification
  3. Post-Silicon Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
  4. Post-Silicon Functional Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    ETS2005: IEEE European Test Symposium, 2005
  5. Evolutionary Optimization: the µGP toolkit
    E. Sanchez, M. Schillaci, G. Squillero
    Hardcover, ISBN 978-0-387-09425-0 / 1st Edition., 2011, XIII, 178 p.
  6. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE DATE2006: Design, Automation and Test in Europe, 2006, pp. 412-417
    BEST PAPER AWARD at IEEE DATE 2006
  7. Anatomy of an extensible evolutionary tool
    E. Sanchez, M. Schillaci, G. Squillero
    GSICE2: II Giornata di Studio Italiana sul Calcolo Evoluzionistico, 2006
  8. On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
    E. Sanchez, M. Sonza Reorda, G. Squillero
    DFT'05: The 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 494-502
  9. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    SBCCI 2005, 18th IEEE Symposium on Integrated Circuits and Systems Design, pp. 74-79
  10. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  11. Evolving Assembly Programs: How Games Help Microprocessor Validation
    F. Corno, E. Sanchez, G. Squillero
    IEEE Transactions on Evolutionary Computation, Special Issue on Evolutionary Computation and Games, Dec. 2005, vol. 9, pp. 695-706
    SILVER MEDAL at the Human-Competitive Awards 2005 (HUMIES)
  12. MicroGP - An Evolutionary Assembly Program Generator
    G. Squillero
    Genetic Programming and Evolvable Machines, vol. 6, no. 3, 2005, pp. 247-263
  13. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    Lecture Notes in Computer Science, Vol 3449, "Applications on Evolutionary Computing: EvoWorkkshops 2005", Lausanne (CH), March 2005, pp. 205-214
  14. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  15. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    International Journal on Artificial Intelligence Tools (IJAIT), Vol. 14, 1-2, Dec. 2004, pp. 897 916
  16. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004
  17. Coupling Different Methodologies to Validate Obsolete Microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  18. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay , E. Sanchez, M. Sonza Reorda, G. Squillero
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, pp. 8-13
  19. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  20. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 871-878
  21. On The Evolution of Corewar Warriors
    F. Corno, E. Sanchez, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 2365-2371
  22. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  23. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    of Evolutionary Computing: EvoWorkshops 2004 proceedings, Coimbra (Portugal), April 5-7 2004, pp. 230-239
  24. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  25. Exploiting Co-Evolution and a Modified Island Model to Climb the Core War Hill
    F. Corno, E. Sanchez, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2222-2229
  26. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25 28, 2003, pp. 113-118
  27. An Enhanced Framework for Microprocessor Test-Program Generation
    F. Corno, G. Squillero
    EUROGP2003: 6th European Conference on Genetic Programming, Essex (UK), April 14-16, 2003, pp. 307-315
  28. Exploiting Auto-Adaptive µGP for Highly Effective Test Programs Generation
    F. Corno, G. Squillero
    ICES2003: The 5th International Conference on Evolvable Systems: From Biology to Hardware, Trondheim (Norway), March 17-20, 2003, pp. 262-273
  29. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  30. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  31. A New Evolutionary Paradigm for Cultivating Cellular Automata for Built-In Self Test of Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    [chapter in] Evolutionary Algorithms for Embedded System Design , edited by R. Drechsler and N. Drechsler, Kluwer Academic Publishers, October 2002, ISBN 1-4020-7276-7, pp.? 143-173
  32. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  33. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  34. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    CEC2002: Congress on Evolutionary Computation, Honolulu, Hawaii (USA), pp. 1486-1491
  35. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoIASP2002: 4rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Kinsale (Ireland), April 2002, pp. 183-189
  36. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  37. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2002: 17th ACM Symposium on Applied Computing, March 2002, Madrid (Spain), pp. 608-611
  38. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  39. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  40. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  41. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  42. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2001: 16th ACM Symposium on Applied Computing, March 2001, Las Vegas (USA), pp. 345-350
  43. GA-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    [chapter in] Telecommunications Optimizations: Heuristic and Adaptive Techniques, edited by D. Corne and M. Oates, Wiley and Sons, August 2000, ISBN 0-471-98855-3, pp. 185-198
  44. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  45. Early power estimation for System-on-Chip designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    PATMOS 2000: International Workshop - Power and Timing Modeling Optimization and Simulation, G? ttingen (Germany), September 2000, pp. 108-117
  46. Behavioral-level Test Vector Generation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000, pp. 21-26
  47. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  48. Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    IJCNN2000: IEEE-INNS-ENNS International Joint Conference Neural Networks, Como (I), July 2000, pp. 577-581
  49. Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406
  50. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    CODES2000: IEEE International Workshop on Hardware/Software Codesign, San Diego (USA), May 2000, pp. 136-140
  51. An Improved Cellular Automata-Based BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    ISCAS2000: IEEE International Symposium on Circuits and Systems, Geneve (CH), May 2000, pp. 76-79
  52. CA-CSTP: A new BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 167-172
  53. System-level Test Bench Generation in a Co-design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 25-30
  54. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  55. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  56. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    ICES2000: Third International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh (UK), April 2000, pp. 31-39
  57. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  58. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 205-213
  59. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 385-389
  60. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  61. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  62. A Peak-Power Estimation Algorithm for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, V. Speranza, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 896-899
  63. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
  64. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 1293-1297
  65. Optimizing Deceptive Functions with the SG-Clans Algorithm
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 2190-2195
  66. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  67. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    EuroEcTel99: R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 182-192
    Special Jury Award for Outstanding Work Presented by a Student or Young Researcher
  68. RT-level TPG Exploiting High-Level Synthesis Information
    S. Chiusano, F. Corno, P. Prinetto
    17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999
  69. Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    DATE99: IEEE Design, Automation & Test in Europe, Munich (Germany), March 1999, pp. 754-755
  70. SymFony: a Hybrid Topological-Symbolic ATPG exploiting RT-level Information
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante, U. Glaeser, H. T. Vierhaus
    IEEE Transactions on Computer-Aided Design, February 1999, Vol. 18, No. 2, pp. 191-202
  71. Exploiting Behavioral Information in Gate-Level ATPG
    S. Chiusano, F. Corno, P. Prinetto
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, December 1998
  72. Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
    F. Corno, J. H. Patel, E. M. Rudnick, M. Sonza Reorda, R. Vietti
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998
  73. VEGA: A Verification Tool Based on Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326
  74. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Sonza Reorda, M. Rebaudengo
    Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, SPIE 1998 Annual Meeting
    Invited paper
  75. A Test Pattern Generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  76. On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
    F. Corno, N. Gaudenzi, P. Prinetto, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  77. Algoritmi da taglio
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
    La Rivista del Vetro, Miller Freeman ed., Milano (Italy), anno 22, n. 2, marzo 1998, pp. 86-98
  78. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    F. Corno, M. Sonza Reorda, G. Squillero
    ICEC98: IEEE International Conference on Evolutionary Computation, May 1998, pp. 575-580
  79. Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
    E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  80. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC98: 13th Annual ACM Symposium on Applied Computing, Atlanta, Georgia (USA), February 1998, pp. 349-355
  81. GA-based Performance Analysis of Network Protocols
    M. Baldi, F. Corno, M. Rebaudengo, G. Squillero
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997, pp. 118-124
  82. Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997
    CV. Ramamoorthy Best Paper Award
  83. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, G. Squillero
    CHARME97: Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montr? al, Quebec, Canada, October 1997, pp. 236-251
  84. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  85. Guaranteeing Testability in Re-encoding for Low Power
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  86. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  87. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
  88. Optimizing Area Loss in Flat Glass Cutting
    S. Bisotto, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    GALESIA97, IEE/IEEE International Conference on Genetic ALgorithms in Engineering Systems: Innovations and Applications, Glasgow (UK), September 1997
  89. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386
  90. Cellular Automata for Sequential Test Pattern Generation
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS97: 15th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1997, pp. 60-65
  91. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
  92. SAARA: a Simulated Annealing Algorithm for Test Pattern Generation for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    SAC97: 12th Annual ACM Symposium on Applied Computing, San Jose, CA (USA), February 1997, pp. 228-232
  93. Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Fourth International Conference on Parallel Problem Solving from Nature, Berlin (Germany), September 1996
  94. Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1996
  95. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Confernce, Washington (USA), October 1996
  96. A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE International Conference On Tools with Artificial Intelligence, Toulouse (F), November 1996
  97. A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Brussels (Belgium), April 1996
  98. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    IEEE Design & Test Conference, Paris (F), March 1996
  99. GALLO: a Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 991-1000
  100. GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 943-951
  101. Uso di Tecniche Evolutive per la Risoluzione di problemi di CAD Elettronico
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Processori Dedicati, a cura di Lanfranco Lopriore, Fabrizio Luccio e Maria Marinaro, Collana CNR/Progetto Finalizzato "Sistemi Informatici e Calcolo Parallelo" diretta da Bruno Fadini, Franco Angeli Editore
  102. A Portable ATPG tool for Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  103. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  104. A PVM tool for Automatic Test Generation on Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  105. A Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    ICEC94: IEEE Conference on Evolutionary Computation, Orlando, FL (USA), June 1994
  106. GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE International Conference on Tools with Artificial Intelligence, New Orleans (USA), November 1994
  107. An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  108. Floorplan Area Optimization using Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    GLS94: 4th IEEE Great Lakes Symposium on VLSI, Notre Dame, IN (USA), March 1994
  109. Exploiting a Workstation Network for Automatic Generation of Test Patterns for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A. R. Meo, E. Veiluva
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  110. Hybrid Genetic Algorithms for the Traveling Salesman Problem
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on Neural Networks and Genetic Algorithms, Innsbruck (A), Aprile 1993, pp.559-566
  111. An Experimental Analysis of effects of Migration in Paralell Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    EWPDP93: IEEE/Euromicro Workshop on Parallel and Distributed Processing, Gran Canaria (E), Gennaio 1993, pp.232-238