CAD

Papers on Diagnosis

  1. Cumulative Embedded Memory Failure Bitmap Display & Analysis
    N. Campanelli, T. Kerekes, P. Bernardi, M. de Carvalho, A. Panariti, M. Sonza Reorda, D. Appello, M. Barone
    IEEE Design and Diagnostic of Electronic Circuits and Systems, Vienna, April 2010, pp. 255-260
  2. Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    IET Computers & Digital Techniques, Vol. 4, N. 2, pp. 104-113, March 2010
  3. Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-scan SoCs
    D. Appello, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 11, p. 1654-1659, NOVEMBER 2009
  4. A Case Study on SoC Low-Cost Silicon Debug and Diagnosis
    D. Appello, P. Bernardi, M. Grosso, M. Rotigni, M. Sonza Reorda, V. Tancorre
    SDD08: 5th IEEE International Workshop on Silicon Debug and Diagnosis, San Diego (CA), USA, April 30th - May 1st, 2008
  5. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vo. 27, No. 3, pp. 570-574, March 2008
  6. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sanchez, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 291-299
  7. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3467-3473
  8. A System-layer Infrastructure for SoC Diagnosis
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers
  9. Embedded Memories Diagnosis: An Industrial Workflow
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    ITC06: IEEE International Test Conference, 2006, Santa Clara (CA), USA
  10. A pattern ordering algorithm for reducing the size of fault dictionaries
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    VTS06: 24th IEEE VLSI Test Symposium, 2006, Berkeley (CA), USA, pp. 386-391
  11. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE DATE2006: Design, Automation and Test in Europe, 2006, pp. 412-417
    BEST PAPER AWARD at IEEE DATE 2006
  12. A new DFM-proactive technique
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'05: 2nd IEEE International Workshop on Silicon Debug and Diagnosis
  13. Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 55-60
  14. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 37-41
  15. Exploiting an Infrastructure IP to Reduce Memory Diagnosis Costs in SoCs
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    ETS 2005: IEEE European Test Symposium, 2005, pp. 202-207
  16. On the Diagnosis of SoCs including multiple Memory Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DDECS 2005: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pp. 75-80
  17. Testing logic cores using a BIST P1500 compliant approach: a case of study
    P. Bernardi, G. Masera, F. Quaglio, M. Sonza Reorda
    DATE2005: Design, Automation and Test in Europe, Designer Track, 2005, pp. 228 - 233
  18. Approaching production diagnostic for BIST-based testing
    D. Appello, P. Bernardi, D. Chindamo, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'04: 1st IEEE International Workshop on Silicon Debug and Diagnosis
  19. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello, P. Bernardi, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    TRP'04: 5th IEEE International Workshop on Test Resource Partitioning
  20. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    Journal of Electronic Testing: Theory and Applications, Volume 20, Issue 1, Kluwer Academic Publishers, Feb 2004, pp. 79-87
  21. An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    ETFA 2003: 9th IEEE International Conference on Emerging Technologies and Factory Automation, Lisbon, Portugal, 16-19 September 2003
  22. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385
  23. A New Methodology for Debugging Embedded Cores
    D. Appello, L. Bouzaida, A. Fudoli, R. Mattiuzzo, R. Kapur, M. Rebaudengo, M. Sonza Reorda
    TRP2002: Test Resource Partitioning Workshop 2002, Baltimore, MD (USA), October, 10-11, 2002
  24. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  25. An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 4, January 1993, pp. 11-17
  26. Tecniche di diagnosi per circuiti sequenziali
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume II, pp. 737-748
  27. Sequential circuit diagnosis based on formal verification techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC92: IEEE International Test Conference, Baltimore, MD (USA), September 1992, pp. 187-196
  28. Cross-fertilizing FSM verification techniques and sequential diagnosis
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC92: IEEE European Design Automation Conference, Hamburg (Germany), September 1992, pp. 306-311