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Papers on Fault Injection

  1. Analysis of SEU Effects in Partially Reconfigurable SoPCs
    L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, M. Porrman
    [accepted for publication on] IEEE NASA/ESA Conference on Adaptive Hardware Systems, June 6-9, 2011
  2. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, Cottbus, Germany, 2011
  3. An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-based FPGAs
    L. Sterpone, N. Battezzati, F. Lima Kastensmidt,
    [accepted for publication on] IEEE Transactions on Nuclear Science
  4. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    N. Battezzati, F. Margaglia, M. Violante, F. Decuzzi, D. Merodio Codinachs, B. Bancelin
    [accepted for publication on] IEEE Transactions on Nuclear Science
  5. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    N. Battezzati, F. Margaglia, M. Violante, F. Decuzzi, D. Merodio Codinachs, B. Bancelin
    IEEE RADECS 2010: 11th European Conference on Radiation and Its Effects on Component and Systems, 2010 [accepted for publication]
  6. Advanced Speeding-up Techniques for SEU Sensitivity Assessment
    M. Grosso, H. Guzman-Miranda
    IEEE International Symposium on Industrial Electronics (ISIE 2010), July 4-7, 2010, Bari, Italy (accepted for publication)
  7. Coping with the Obsolescence of Safety- or Mission-Critical Embedded Systems using FPGAs
    H. Guzman-Miranda, L. Sterpone, M. Violante, M. A. Aguirre, M. Gutierrez-Rizo M.
    IEEE Transactions on Industrial Electronics, Vol. 58, Issue 3, pp. 814 - 821, 2011
  8. Analysis of SET Propagation in Flash-based FPGAs by means of Electrical Pulse Injection
    L. Sterpone, N. Battezzati, V. Ferlet-Cavrois
    IEEE Transactions on Nuclear Science, Vol. 57, Issue 4, Part 1, pp. 1820 - 1826, 2010
  9. Monte Carlo Analysis of the Effects of Soft Error Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Volume 55, Issue 6, Part 1, December 2008, pp. 3381 - 3387
  10. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. DAngelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2267 - 2273
  11. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    IEEE NASA/ESA Conference on Adaptive Hardware and Systems, June 22-25, 2008, Noordwijk, The Netherlands, pp. 157 - 163
  12. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2019 - 2027
  13. A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
    N. Battezzati, L. Sterpone, M. Violante
    CF2008: ACM International Conference on Computing Frontiers, Ischia, Italy, 5 - 7 May 2008, pp. 347 - 352
  14. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008: IEEE International Symposium on Industrial Electronics, Cambridge, UK, 30 June - 2 July 2008, pp. 2282 - 2287
  15. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 1968 - 1973
  16. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2063 - 2069
  17. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    E. L. Rhod, C. A. Lang Lisb?a, L. Carro, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, Volume 24, Numbers 1-3, June 2008, pp. 45 - 56
  18. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, 2008, pp. 35 - 44
  19. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    L. Sterpone, M. Aguirre, J. Tombs, H. Guzman
    DATE 2008: IEEE Design, Automation and Test in Europe, 2008, pp. 336 - 341
  20. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE Transactions on Nuclear Science, Vol. 54, No. 6, Part 1, December 2007, pp. 2576-2583
  21. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  22. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  23. A new approach to estimate the effect of single event transients in complex circuits
    M. A. Aguirre, V.Baena, J. Tombs, M. Violante
    [accepted for publication on] IEEE Transactions on Nuclear Science, 2007
  24. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, pages 965 - 970
  25. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. A. Maestro, O. Ruano, P. Reviriego
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 261 - 266
  26. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 159 - 164
  27. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, Pages 965 - 970
  28. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 23, No. 1, February, 2007, pp. 47 - 54
  29. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, December 2006, pp. 3550 - 3557
  30. Online hardening of programs against SEUs and SETs
    C.A.L. Lisboa, L. Carro, M. Sonza Reorda, M. Violante
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 280 - 290
  31. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265 - 273
  32. Hardware-in-the-loop-based Dependability Analysis of Automotive Systems
    M. Sonza Reorda, M. Violante
    IOLTS06: IEEE International On-Line Testing Symposium, 2006, Como, Italy, pp. 229-234
  33. Dependability evaluation of transient fault effects in Reconfigurable Compute Fabric devices
    L. Sterpone, M. Violante
    IOLTS2006, IEEE 12th International On-Line Testing Symposium , 2006, pp. 189 - 190
  34. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    IEEE Transactions on Nuclear Science, Vol. 53, Issue 4, August 2006, pp. 2054 - 2059
  35. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82
  36. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744
  37. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    IEEE Design & Test of Computers, Vol. 23, No. 1, Jan/Feb. 2006, pp. 38-45
  38. A New Hybrid Fault Detection Technique for Systems-on-a-Chip
    P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198
  39. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 68-73
  40. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IEEE Dependable Systems and Networks Symposium, july 2005, pp. 50 -58
  41. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223
  42. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549
  43. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    RADECS 2005: 8th European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1 - J5-4
  44. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150
  45. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59
  46. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
    BEST PAPER AWARD at IEEE ETS 2005
  47. On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DATE2005: IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295
  48. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  49. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S.Tosato
    ITC2004: IEEE International Test Conference, Charlotte (NC), USA, October 24-30, 2004, pp. 1332-1339
  50. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432
  51. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 20, August 2004, pp. 433-437
  52. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75
  53. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 79-84
  54. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120
  55. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    Journal of Systems Architecture, Elsevier Science, Amsterdam, Netherland, Vol. 50, No. 5, 2004, pp. 239-246
  56. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  57. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  58. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  59. Accurate single-event-transient analysis via zero-delay logic simulation
    M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2113-2118
  60. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 5, October 2003, pp. 577-584
  61. Accurate Dependability Analysis of CAN-based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    SBCCI2003: 16th IEEE Symposium on Integrated Circuits and Systems Design, 2003, pp. 337-342
  62. Relating Vehicle-level and Network-level Reliability through High-level Fault Injection
    F. Corno, P. Gabrielli, S. Tosato
    HLDVT2003: IEEE International Workshop on High Level Design Validation and Test, 2003
  63. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda, M. Violante
    FPL2003: International Conference on Field Programmable Logic and Application, 2003, pp. 616-626
  64. Detailed comparison of dependability analyses performed at RT and gate levels
    A. Ammari, R. Leveugle, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 336-343
  65. Dependability Analysis of CAN Networks: an emulation-based approach
    J. Perez, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp 537-544
  66. System-level Analysis of Fault Effects in an Automotive Environment
    F. Corno, P. Gabrielli, S. Tosato
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  67. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Microelectronics Journal, Vol. 34, No. 1, January 2003, pp. 53-61, Elsevier Science, Amsterdam, Netherland.
  68. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    M. Violante, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  69. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123
  70. A Method to Study Active Brake System Reliability
    G. Repici, G. Sembenini, A. Sorniotti, S. Tosato
    3rd AED International Conference, Prague
  71. UML-Based System-Level specifications for integrated systems
    F. Corno, P. Maggiore, G. Repici, A. Sorniotti, E. Suraci, S. Tosato, M. Velardocchia
    9th EAEC International Congress, "European Automotive Industry Driving Global Changes"
  72. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  73. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607
  74. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco
    IEEE Transactions on Nuclear Science, Vol. 49, No. 3, June 2002, pp. 1491-1495
  75. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271
  76. A simplified gate-level fault model for crosstalk effects analysis
    P. Civera, L. Macchiarulo, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 31-39
  77. Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
    M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 263-271
  78. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL2002: International Conference on Field Programmable Logic and Application, 2002, pp. 607-615
  79. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  80. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 206-210
  81. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  82. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  83. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  84. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
  85. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  86. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  87. Effectiveness and limitations of various software techniques for "soft error" detection: A comparative study
    B. Nicolescu, R. Velazco, M. Sonza Reorda
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001
  88. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  89. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  90. Early evaluation of bus interconnects dependability for System-on-Chip Designs
    M. Lajolo, M. Sonza Reorda, M. Violante
    14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
  91. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  92. Dependability Evaluation through Effective Fault Injection Techniques on VHDL Descriptions
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    ISATA 2000: Automotive and Transportation Technology, Dublin (Ireland), September 2000, pp. 171-179
  93. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    19th International Conference on Computer Safety, Reliability and Security, Safecomp 2000, Rotterdam, The Nederlands, October 2000, pp. 27-36
  94. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 61-66
  95. Evaluating System Dependability in a Co-Design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 586-590
  96. FlexFi: a flexible Fault Injection environment for microprocessor-based systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    SAFECOMP 1999: 18th International Conference on Computer Safety, Reliability and Security, (Lecture Notes in Computer Science, Springer Verlag, A. Pasquini (Ed.)), pp. 323-335
  97. Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
    M. Rebaudengo, M. Sonza Reorda
    VTS99: 17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999, pp. 452-457
  98. A Low-Cost Programmable Board for Speeding-Up Fault Injection in Microprocessor-Based Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda
    RAMS99: Annual Reliability and Maintainability Symposium, Washington, DC (USA), January 1999, pp. 171-177
  99. Fault Injection for Embedded Microprocessor-based Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    Journal of Universal Computer Science (Special Issue on Dependability Evaluation and Validation), Vol. 5, No. 5, pp. 693-711
  100. A Fault Injection Environment for Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC98: IEEE International Test Conference, Washington (USA), September 1998, pp. 768-773
  101. EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ACM Transactions on Design Automation of Electronic Systems, Vol. 3, Number 4, October 1998, pp. 626-634
  102. An Integrated HW and SW Fault Injection Environment for Real-Time Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda, P. L. Civera
    DFT98, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2-4 1998, Austin, Texas, pp. 117-122
  103. Exploiting the Background Debugging Mode in a Fault Injection system
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IPDS: The 3rd Annual IEEE International Computer Performance & Dependability Symposium, Durham (NC), September 7-9 1998, pag. 277
  104. A Hybrid Fault Injection Methodology for Real Time Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda, A. Ferro
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 74-75
  105. Fault-List Collapsing for Fault Injection Experiments
    A. Benso, M. Rebaudengo, L. Impagliazzo, P. Marmo
    RAMS98: Annual Reliability and Maintainability Symposium, Anaheim, CA (USA), January 1998, pp. 383-388
  106. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
    DFT97: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris (F), November 1997
  107. A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Ubar
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997
  108. Faulty Behavior Observation on a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  109. Il ruolo delle tecniche di fault injection nell'analisi dell'affidabilit? dei sistemi
    A. Benso, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    AEI (Automazione Energia Informazione), Vol. 83, N. 10, Ottobre 1996, pp. 63/807-69/813