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Papers on Fault Tolerance

  1. A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification
    M. Di Marzio, M. Grosso, M. Sonza Reorda, L. Sterpone, G. Audisio, M. Sabatini
    IEEE International Symposium on Circuits and Systems, pp. 865 - 868, 2010
  2. A new Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
    L. Sterpone
    ACM Transactions on Reconfigurable Technology and Systems, Vol. 4, Issue 1, A7, pp. 1 - 21, December 2010
  3. A New Placement Algorithm for the Mitigation of Multiple Cell Upsets in SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    DATE2010: IEEE Design, Automation and Test in Europe, 2010, Dresden, Germany, pp. 1231 - 1236
  4. On the Static Cross Section of SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Radiation Effects Data Workshop, July 2008, pp. 94 - 97
  5. Electronics System Design Techniques for Safety Critical Applications
    L. Sterpone
    Series: Lecture Notes in Electrical Engineering, Vol. 26, Springer, London (UK), ISBN 978-1-4020-8978-7
    EDAA Outstanding dissertation Award 2007
  6. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    E. L. Rhod, C. A. Lang Lisb?a, L. Carro, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, Volume 24, Numbers 1-3, June 2008, pp. 45 - 56
  7. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  8. Safety Evaluation of NanoFabrics
    M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 418-426
  9. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani, P. Bernardi, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 342-347
  10. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi, L. Bolzani, M. Sonza Reorda
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 107-112
  11. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265 - 273
  12. Software-Implemented Hardware Fault Tolerance
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Springer Science+Business Media, LLC, New York (USA), ISBN: 0-387-26060-9, pages 228
  13. Hardening FPGA-based systems against SEUs: A new design methodology
    L. Sterpone, M. Violante
    Academy Publisher Journal of Computers, Vol. 1, No. 1, April 2006, pp. 22 - 30
  14. A new approach to cope with single event upsets in processor-based systems
    M. Schillaci, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 145-150
  15. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2005: The Annual Reliability and Maintainability Symposium, 2005, Session 14B
  16. Software Techniques for Dependable Computer-based Systems
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Space radiation environment and its effects on spacecraft components and systems", C padu s d., Toulouse (France), ISBN 2-85428-654-5, 2004, pp. 461-480
  17. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 20, August 2004, pp. 433-437
  18. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 79-84
  19. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    LATW'04: IEEE Latin-American Test WorkShop
  20. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581-588
  21. Introducing SW-Based Fault Handling Mechanisms to cope with EMI in Embedded Electronics: are they a good remedy?
    F. Vargas, D. Brum, D. Prestes, L. Bolzani, E. Rhod, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  22. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  23. A new Software-based technique for low-cost Fault-Tolerant application
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2003: The Annual Reliability and Maintainability Symposium, 2003, pp. 25-28
  24. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante
    SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 101-106
  25. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  26. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    LATW2002: IEEE Latin American Test Workshop, 2002
  27. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  28. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  29. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  30. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    SCAM, IEEE International Workshop on Source Code Analysis and Manipulation, 2001, pp. 33-42
  31. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  32. Exploring Test Solutions by means of System-level Design Tools
    M. Lajolo, M. Sonza Reorda, M. Violante
    DCIS, Design of Circuits and Integrated Systems, 2001
  33. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  34. Effectiveness and limitations of various software techniques for "soft error" detection: A comparative study
    B. Nicolescu, R. Velazco, M. Sonza Reorda
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001
  35. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  36. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  37. Early evaluation of bus interconnects dependability for System-on-Chip Designs
    M. Lajolo, M. Sonza Reorda, M. Violante
    14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
  38. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  39. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT'00, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2000, pp. 257-265
  40. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 17-20
  41. Soft-error Detection through Software Fault-Tolerance techniques
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 210-218
  42. Evaluating cost and effectiveness of software redundancy techniques for hardware errors detection
    M. Rebaudengo, M. Sonza Reorda
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 88-89