Papers on Fault-Tolerance

1. An integrated flow for the design of hardened circuits on SRAM-based FPGAs
   C. Bolchini, A. Miele, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante
   15th IEEE European Test Symposium (ETS), 2010, pp. 214 - 219
2. Advanced technologies for transient faults detection and compensation
   M. Sonza Reorda, L. Sterpone, M. Violante
   book chapter on IGI [accepted for publication on]
3. Layout-aware Multi-Cell Upsets Effects Analysis on TMR circuits implemented on SRAM-based FPGAs
   L. Sterpone, M. Violante, A. Panariti, A. Bocquillon, F. Miller, N. Buard, A. Manuzzato, S. Gerardin, A. Paccagnella
   IEEE Transactions on Nuclear Science [accepted for publication on]
4. Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications
   N. Battezzati, L. Sterpone, M. Violante
   Springer, 1st Edition, 240 pages, ISBN: 978-1-4419-7594-2