Papers on HW/SW Codesign

1. Automatic Generation of Validation Stimuli for Application-Specific Processors
   O. Goloubeva, M. Sonza Reorda, M. Violante
   DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
2. Early evaluation of bus interconnects dependability for System-on-Chip Designs
   M. Lajolo, M. Sonza Reorda, M. Violante
   14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
3. Early power estimation for System-on-Chip designs
   M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
   PATMOS 2000: International Workshop - Power and Timing Modeling Optimization and Simulation, G? ttingen (Germany), September 2000, pp. 108-117
4. Behavioral-level Test Vector Generation for System-on-Chip Designs
   M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
   IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000, pp. 21-26
5. Automatic Test Bench Generation for Simulation-based Validation
   M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
   CODES2000: IEEE International Workshop on Hardware/Software Codesign, San Diego (USA), May 2000, pp. 136-140
6. System-level Test Bench Generation in a Co-design Framework
   M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
   ETW2000: European Test Workshop, May 2000, pp. 25-30