CAD

Papers on Nanometric Technologies

  1. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, December, 2009, Vol. 56, pp. 3534 - 3541
  2. Monte Carlo Analysis of the Effects of Soft Error Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Volume 55, Issue 6, Part 1, December 2008, pp. 3381 - 3387
  3. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE Transactions on Nuclear Science, Vol. 54, No. 6, Part 1, December 2007, pp. 2576-2583
  4. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  5. A new approach to estimate the effect of single event transients in complex circuits
    M. A. Aguirre, V.Baena, J. Tombs, M. Violante
    [accepted for publication on] IEEE Transactions on Nuclear Science, 2007
  6. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, pages 965 - 970
  7. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. A. Maestro, O. Ruano, P. Reviriego
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 261 - 266
  8. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 159 - 164
  9. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, Pages 965 - 970
  10. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, December 2006, pp. 3550 - 3557
  11. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223
  12. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549
  13. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    RADECS 2005: 8th European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1 - J5-4
  14. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  15. Exploiting an I-IP for In-field SOC test
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 404-412
  16. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120
  17. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    Journal of Systems Architecture, Elsevier Science, Amsterdam, Netherland, Vol. 50, No. 5, 2004, pp. 239-246
  18. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  19. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  20. Accurate single-event-transient analysis via zero-delay logic simulation
    M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2113-2118
  21. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 5, October 2003, pp. 577-584
  22. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda, M. Violante
    FPL2003: International Conference on Field Programmable Logic and Application, 2003, pp. 616-626
  23. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25 28, 2003, pp. 113-118
  24. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Microelectronics Journal, Vol. 34, No. 1, January 2003, pp. 53-61, Elsevier Science, Amsterdam, Netherland.
  25. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385
  26. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    M. Violante, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  27. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123
  28. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  29. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  30. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 720-725
  31. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607