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Papers on Reliability

  1. Coping with the Obsolescence of Safety- or Mission-Critical Embedded Systems using FPGAs
    H. Guzman-Miranda, L. Sterpone, M. Violante, M. A. Aguirre, M. Gutierrez-Rizo M.
    IEEE Transactions on Industrial Electronics, Vol. 58, Issue 3, pp. 814 - 821, 2011
  2. On the Mitigation of SET broadening effects in Integrated Circuits
    L. Sterpone, N. Battezzati
    IEEE Design and Diagnostic of Electronic Circuits and Systems, pp. 36 - 39, 2010
  3. Analysis of SET Propagation in Flash-based FPGAs by means of Electrical Pulse Injection
    L. Sterpone, N. Battezzati, V. Ferlet-Cavrois
    IEEE Transactions on Nuclear Science, Vol. 57, Issue 4, Part 1, pp. 1820 - 1826, 2010
  4. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, December, 2009, Vol. 56, pp. 3534 - 3541
  5. Gene expression reliability estimation through cluster-based analysis
    L. Sterpone, A. Benso, S. Di Carlo, G. Politano
    MEMEA 2009: IEEE International Conference on Medical Measurements and Applications, Cetraro, Italy, 29 - 30 May, 2009, pp. 229 - 231
  6. Evaluating Alpha-induced Soft Errors in Embedded Microprocessors
    P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello
    IOLTS 2009: 15th IEEE International On-line Testing Symposium, Sesimbra-Lisbon, Portugal, 2009, pp. 69-74
  7. DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
    D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
    27th IEEE VLSI Test Symposium (VTS 09), May 3 - 7, 2009, Santa Cruz, CA, USA, pp. 276-281
  8. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    ETS 2009: 14th IEEE European Test Symposium, Sevilla, Spain, 2009, pp. 93-98
  9. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020, Santa Clara (CA), USA, October 30-31, 2008
  10. An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso
    ETS 2008: 13th IEEE European Test Symposium, Verbania, Italy, 2008, pp. 140 - 145
  11. Monte Carlo Analysis of the Effects of Soft Error Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Volume 55, Issue 6, Part 1, December 2008, pp. 3381 - 3387
  12. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    W. J. Perez, J. Velasco-Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    14th IEEE International On-Line Testing Symposium, 2008, pp. 143-148
  13. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, M. Violante
    14th IEEE International On-Line Testing Symposium , 22 - 25 June, 2008, pp. 157 - 163
  14. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. DAngelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2267 - 2273
  15. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    IEEE NASA/ESA Conference on Adaptive Hardware and Systems, June 22-25, 2008, Noordwijk, The Netherlands, pp. 157 - 163
  16. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2019 - 2027
  17. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 1968 - 1973
  18. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2063 - 2069
  19. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, 2008, pp. 35 - 44
  20. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    L. Sterpone, M. Aguirre, J. Tombs, H. Guzman
    DATE 2008: IEEE Design, Automation and Test in Europe, 2008, pp. 336 - 341
  21. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE Transactions on Nuclear Science, Vol. 54, No. 6, Part 1, December 2007, pp. 2576-2583
  22. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  23. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 96 - 104
  24. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 79 - 86
  25. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani, P. Bernardi, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 342-347
  26. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi, L. Bolzani, M. Sonza Reorda
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 107-112
  27. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  28. A new approach to estimate the effect of single event transients in complex circuits
    M. A. Aguirre, V.Baena, J. Tombs, M. Violante
    [accepted for publication on] IEEE Transactions on Nuclear Science, 2007
  29. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, pages 965 - 970
  30. Extended Fault Detection Techniques for Systems-on-Chip
    P. Bernardi, L. Bolzani, M. Sonza Reorda
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 55-60
  31. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. A. Maestro, O. Ruano, P. Reviriego
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 261 - 266
  32. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 159 - 164
  33. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, Pages 965 - 970
  34. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    L. Sterpone, M. Violante
    ISIE2007: IEEE International Symposium on Industrial Electronics, Vigo, Spain, June 4-7, 2007, pp. 3345 - 3349
  35. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, December 2006, pp. 3550 - 3557
  36. Hardware-in-the-loop-based Dependability Analysis of Automotive Systems
    M. Sonza Reorda, M. Violante
    IOLTS06: IEEE International On-Line Testing Symposium, 2006, Como, Italy, pp. 229-234
  37. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82
  38. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744
  39. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    IEEE Design & Test of Computers, Vol. 23, No. 1, Jan/Feb. 2006, pp. 38-45
  40. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436 - 444
  41. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223
  42. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549
  43. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    RADECS 2005: 8th European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1 - J5-4
  44. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150
  45. Integrating BIST techniques for on-line SoC testing
    A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 235-240
  46. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59
  47. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
    BEST PAPER AWARD at IEEE ETS 2005
  48. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  49. Software Techniques for Dependable Computer-based Systems
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Space radiation environment and its effects on spacecraft components and systems", C padu s d., Toulouse (France), ISBN 2-85428-654-5, 2004, pp. 461-480
  50. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S.Tosato
    ITC2004: IEEE International Test Conference, Charlotte (NC), USA, October 24-30, 2004, pp. 1332-1339
  51. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    Journal of Systems Architecture, Elsevier Science, Amsterdam, Netherland, Vol. 50, No. 5, 2004, pp. 239-246
  52. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  53. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  54. Accurate single-event-transient analysis via zero-delay logic simulation
    M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2113-2118
  55. A General Method to Study Complex System Reliability
    G. Repici, G. Sembenini, A. Sorniotti, S. Tosato
    3rd AED International Conference, Prague
  56. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  57. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
  58. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  59. Exploring Test Solutions by means of System-level Design Tools
    M. Lajolo, M. Sonza Reorda, M. Violante
    DCIS, Design of Circuits and Integrated Systems, 2001
  60. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  61. Effectiveness and limitations of various software techniques for "soft error" detection: A comparative study
    B. Nicolescu, R. Velazco, M. Sonza Reorda
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001
  62. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  63. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  64. Early evaluation of bus interconnects dependability for System-on-Chip Designs
    M. Lajolo, M. Sonza Reorda, M. Violante
    14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
  65. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  66. Il ruolo delle tecniche di fault injection nell'analisi dell'affidabilit? dei sistemi
    A. Benso, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    AEI (Automazione Energia Informazione), Vol. 83, N. 10, Ottobre 1996, pp. 63/807-69/813
  67. On-line Testing of an Off-the-Shelf Microprocessor Board for Safety-critical Applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
    EDCC Conference, Taormina (Italy), October 1996