CAD

Papers on Rt-Level

  1. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 71 - 76
  2. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3474-3481
  3. Coupling EA and High-level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L.Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    GECCO2007: Genetic and Evolutionary Computation Conference, London, UK, July 7-11, 2007, pp. 1912-1919
  4. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 348-353
  5. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 265-270
  6. On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  7. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  8. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    International Journal on Artificial Intelligence Tools (IJAIT), Vol. 14, 1-2, Dec. 2004, pp. 897 916
  9. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  10. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  11. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  12. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  13. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  14. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  15. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  16. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  17. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  18. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  19. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  20. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  21. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero
    DCIS2001: Design of Circuits and Integrated Systems, 2001, pp. 273-278
  22. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  23. Dependability Evaluation through Effective Fault Injection Techniques on VHDL Descriptions
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    ISATA 2000: Automotive and Transportation Technology, Dublin (Ireland), September 2000, pp. 171-179
  24. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    HLDVT2000: IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000
  25. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830
  26. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    19th International Conference on Computer Safety, Reliability and Security, Safecomp 2000, Rotterdam, The Nederlands, October 2000, pp. 27-36
  27. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  28. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 61-66
  29. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  30. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 205-213
  31. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 385-389
  32. High-level ATPG: a real topic or an academic amusement?
    M. Sonza Reorda
    IEEE International Test Conference, Atlantic City (USA), September 1999, Poster Session, pp. 1118
  33. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  34. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
  35. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    EuroEcTel99: R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 182-192
    Special Jury Award for Outstanding Work Presented by a Student or Young Researcher
  36. RT-level TPG Exploiting High-Level Synthesis Information
    S. Chiusano, F. Corno, P. Prinetto
    17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999
  37. Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
    E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  38. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
  39. Testable Synthesis through RT-level DfT rules
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda, M. Violante
    ED&TC97: IEEE European Design and Test Conference User's Forum, Paris (F), March 1997, pp. 57-61
  40. Faulty Behavior Observation on a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  41. Fault Tolerant and BIST design of a FIFO cell
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  42. A Process Algebra Interpretation of a Verification Oriented Overlanguage of VHDL
    C. Bayol, B. Soulas, F. Corno, P. Prinetto, D. Borrione
    EURO-DAC94: IEEE European Design Automation Conference, Grenoble (F), September 1994
  43. VOVHDL: a verification-oriented dialect of VHDL
    P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
    VFE93: VHDL-Forum for CAD in Europe, Hamburg (D), September 1993, pp. 37-47
  44. A Methodology for System-Level Design for Verifiability
    P. Camurati, F. Corno, P. Prinetto
    CHARME93: Advanced Research Workshop on Correct Hardware Design Methodologies, Arles (F), May 1991, (Lecture Notes in Computer Science, Springer Verlag, Berlin (Germany), n. 683), pp. 80-91