CAD

Papers on Single Event Effects

  1. Coping with the Obsolescence of Safety- or Mission-Critical Embedded Systems using FPGAs
    H. Guzman-Miranda, L. Sterpone, M. Violante, M. A. Aguirre, M. Gutierrez-Rizo M.
    IEEE Transactions on Industrial Electronics, Vol. 58, Issue 3, pp. 814 - 821, 2011
  2. Analysis of SET Propagation in Flash-based FPGAs by means of Electrical Pulse Injection
    L. Sterpone, N. Battezzati, V. Ferlet-Cavrois
    IEEE Transactions on Nuclear Science, Vol. 57, Issue 4, Part 1, pp. 1820 - 1826, 2010
  3. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    19th IEEE International Conference on Field Programmable Logic and Applications, August 31 - September 2, 2009, pp. 723 - 724
  4. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs
    N. Battezzati, F. Decuzzi, M. Violante, M. Briet
    15th IEEE International On-Line Testing Symposium, 24 - 26 June, 2009, pp. 89 - 94
  5. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    F. Abate, F. Lima Kastensmidt, L. Sterpone, M. Violante
    IEEE Design, Automation and Test in Europe, Munich, Germany , 20 - 24 April 2009, pp. 1226 - 1229
  6. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. DAngelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2267 - 2273
  7. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    IEEE NASA/ESA Conference on Adaptive Hardware and Systems, June 22-25, 2008, Noordwijk, The Netherlands, pp. 157 - 163
  8. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2019 - 2027
  9. A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
    N. Battezzati, L. Sterpone, M. Violante
    CF2008: ACM International Conference on Computing Frontiers, Ischia, Italy, 5 - 7 May 2008, pp. 347 - 352
  10. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008: IEEE International Symposium on Industrial Electronics, Cambridge, UK, 30 June - 2 July 2008, pp. 2282 - 2287
  11. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 1968 - 1973
  12. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2063 - 2069