Papers on System-Level

1. UML-Based System-Level specifications for integrated systems
   F. Corno, P. Maggiore, G. Repici, A. Sorniotti, E. Suraci, S. Tosato, M. Velardocchia
   9th EAEC International Congress, "European Automotive Industry Driving Global Changes"
2. Early power estimation for System-on-Chip designs
   M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
   PATMOS 2000: International Workshop - Power and Timing Modeling Optimization and Simulation, G? ttingen (Germany), September 2000, pp. 108-117
3. A new Functional Fault Model for System-Level Descriptions
   P. Camurati, F. Corno, M. Meo, P. Prinetto
   VTS94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994
4. System-Level Modeling and Verification: a Comprehensive Design Methodology
   P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
   ED&TC94: 1st IEEE European Design and Test Conference 1994, Paris, February 1994
5. A verifiable design methodology at system-level
   P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
   ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 364-367
6. An efficient tool for system-level verification of behaviors and temporal properties
   P. Camurati, F. Corno, P. Prinetto
   EURO-DAC93: IEEE European Design Automation Conference, Hamburg (Germany), September 1993, pp. 124-129
7. A Methodology for System-Level Design for Verifiability
   P. Camurati, F. Corno, P. Prinetto
   CHARME93: Advanced Research Workshop on Correct Hardware Design Methodologies, Arles (F), May 1991, (Lecture Notes in Computer Science, Springer Verlag, Berlin (Germany), n. 683), pp. 80-91
8. System-Level Fault Modeling and Test Pattern Generation with Process Algebras
   P. Camurati, F. Corno, P. Prinetto
   ETC93: IEEE European Test Conference, Rotterdam (NL), April 1993, pp. 47-56