Publications

Authors
Title
Journal \ Conference details
L. Sterpone, D. Sabena, M. Sonza Reorda A New Fault Injection Approach for Testing Network-on-Chips PDP 2012, Munich. pp. 530-535.
L. Sterpone, D. Sabena, M. Sonza Reorda A New SBST Algorithm for Testing the Register File of VLIW Processors IEEE Design, Automation and Test in Europe, 2012, Dresden, Germany, 12-16 March 2012. 412 -417.
Sabena D., Sonza Reorda M., Sterpone L. On the development of Software-Based Self-Test methods for VLIW processors Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on, Austin, TX, USA, October, 2012.. pp. 25-30.
Sabena D., Sonza Reorda M., Sterpone L. On the optimized generation of Software-Based Self-Test programs for VLIW processors VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International Conference on, Santa Cruz, CA, USA, 7-10 October 2012. pp. 129-134.
J. Hagemeyer, A. Hilgenstein, D. Jungewelter, D. Cozzi, C. Felicetti, U. Rueckert, S. Korf, M. Koester, F. Margaglia, M. Porrmann, F. Dittmann, M. Ditze, J. Harris, L. Sterpone, J. Ilstad A scalable platform for run-time reconfigurable satellite payload processing Adaptive Hardware and Systems, Erlangen (GERMANY), June 25 - 28, 2012. pp. 9-16.
Sabena D., Sonza Reorda M., Sterpone L. On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, April 2013.
Sabena D., Sonza Reorda M., Sterpone L. On the Development of Diagnostic Test Programs for VLIW Processors VLSI and System-on-Chip (VLSI-SoC), 2013 IEEE/IFIP 21th International Conference on, Istanbul (TURKEY),pp. 84-89, 7-9 October 2013.
P. Rech, L. L. Pilla, F. Silvestri, C. Frost, P. O. A. Navaux, M. Sonza Reorda, and L. Carro Neutron Sensitivity and Hardening Strategies for Fast Fourier Transform on GPUs Radiation Effects on Components and Systems (RADECS), London (UK), September 2013.
Sabena D., Sonza Reorda M., Sterpone L., Rech P., Carro L. On the evaluation of soft-errors detection techniques for GPGPUs 2013 8th International Design and Test Symposium (IDT), Marrakech (Morocco), December 2013
R. Ferreira, V. Duarte, W. Meireles, M Pereira, L. Carro, S. Wong A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained Reconfigurable Architectures (July 2013) International Conference on Embedded Computer Systems: Architecture Modeling and Simulation (IC-SAMOS 2013), 15-18 July 2013, Samos, Greece
R. Ferreira, L. Rocha, A. Santos, J. Nacif, S. Wong, L. Carro A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS (September 2013) 23nd International Conference on Field Programmable Logic and Applications (FPL 2013), 2-4 September 2013, Porto, Portugal, FPL Michael Servit Memorial (Best Paper) Award
A.A.C. Brandon, S. Wong Support for dynamic issue width in VLIW processors using generic binaries (March 2013) Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France
F. Anjam, S. Wong Configurable Fault-tolerance for a Configurable VLIW Processor (March 2013) 9th International Symposium on Applied Reconfigurable Computing (ARC 2013), 25-27 March 2013, Los Angeles, USA
P.C. Santos, G.L. Nazar, F. Anjam, S. Wong, D. Matos, L. Carro A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of Total Reconfiguration (January 2013) 7th HiPEAC Workshop on Reconfigurable Computing (WRC 2013), 21 January 2013, Berlin, Germany
P.C. Santos, G.L. Nazar, F. Anjam, S. Wong, D. Matos, L. Carro A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of a Multi-Level Reconfiguration (January 2013), 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM 2013), 22 January 2013, Berlin, Germany
P.C. Santos, G.L. Nazar, F. Anjam, S. Wong, L. Carro Adapting Communication for Adaptable Processors: A Multi-Axis Reconfiguration Approach (December 2012), International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), 5-7 December 2012, Cancun, Mexico
F. Anjam, L. Carro, S. Wong, G.L. Nazar, M.B. Rutzig Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor (July 2012), International Conference on Embedded Computer Systems: Architecture Modeling and Simulation (IC-SAMOS 2012), 16-19 July 2012, Samos, Greece
F. Anjam, Q. Kong, R.A.E. Seedorf, S. Wong A Run-time Task Migration Scheme for an Adjustable Issue-slots Multi-core Processor (March 2012), 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), 19-23 March 2012, Hong Kong, China
F. Anjam, Q. Kong, R.A.E. Seedorf, S. Wong A Run-time Task Migration Scheme for an Adjustable Issue-slots Multi-core Processorf (March 2012), 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), 19-23 March 2012, Hong Kong, China
F. Anjam, Q. Kong, R.A.E. Seedorf, S. Wong On the Implementation of Traps for a Softcore VLIW Processorf (January 2012), 6th HiPEAC Workshop on Reconfigurable Computing (WRC 2012), 24 January 2012, Paris, France
R.A.E. Seedorf, F. Anjam, A.A.C. Brandon, S. Wong Design of a Pipelined and Parameterized VLIW Processor: _-VEX v.2 (January 2012), 6th HiPEAC Workshop on Reconfigurable Computing (WRC 2012), 24 January 2012, Paris, France
R., Parizi R., Carro L., Moreira A. Compiler Optimizations Impact the Reliability of the Control-Flow of Radiation-Hardened Software Journal of Aerospace Technology and Management (Online), v. 5, p. 323-334, 2013
Parizi Rafael B., Ferreira Ronaldo R., Carro Luigi, Moreira Álvaro F. Compiler Optimizations Do Impact the Reliability of Control-Flow Radiation Hardened Embedded Software IFIP Advances in Information and Communication Technology. 1ed.: Springer Berlin, Heidelberg, 2013, v. 403, p. 49-60.
Ferreira Ronaldo R., ROLT J., NAZAR G. L., Moreira AF., CARRO L. MoMa: A Radiation Hardened Architecture based on Branch-Free Control-Flow Resolution and on Transactional Data-Path Execution Intel Compiler, Architecture and Tools Conference, 2013, Haifa (Israel), 2013.
ITTURRIET, F. ; NAZAR, G. L. ; Ferreira, R ; Moreira, Álvaro F. ; Carro, Luigi Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems ACM T RECONFIG TECHN, 2013.
NAZAR, GABRIEL L. ; RECH, PAOLO ; FROST, CHRISTOPHER ; Carro, Luigi Radiation and Fault Injection Testing of a Fine-Grained Error Detection Technique for FPGAs IEEE Transactions on Nuclear Science, v. 60, p. 1-1, 2013.
TABORDA, T. B. ; NAZAR, G. L. ; CARRO, L. Investigating Reliability-Critical Components of VLIW Processors 5th Workshop on Design for Reliability (DFR 2013), 2013, Berlin (Germany), Workshop on Design for Reliability (DFR), 2013.
NAZAR, G. L. ; SANTOS, L. P. ; CARRO, L. Accelerated FPGA Repair through Shifted Scrubbing International Conference on Field Programmable Logic and Applications (FPL), 2013, Porto. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). Piscataway: IEEE, 2013.
SANTOS, L. P. ; NAZAR, G. L. ; CARRO, L. Dynamically Shifted Scrubbing for Fast FPGA Repair In: 2nd Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2013, Porto. Proceedings of the 2nd Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2013.
NAZAR, G. L. ; SANTOS, L. P. ; CARRO, L. Scrubbing Unit Repositioning for Fast Error Repair in FPGAs International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), 2013, Montreal. Proceedings of the International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), 2013.
Santos, P; Nazar, G. Carro, L. Adapting Communication for Adaptable Processors: A Multi-Axis Reconfiguration Approach ReConFig-2012
Santos, P; Stoffel, J., Carro, L. A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of a Multi-Level Reconfiguration DITAM-2013, Berlin (Germany)
Cassano, Luca ; Cozzi, Dario ; Korf, Sebastian ; Hagemeyer, Jens ; Porrmann, Mario ; Sterpone, Luca On-line testing of permanent radiation effects in reconfigurable systems Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp. 717-720
Sterpone, L. ; Ullah, A. On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on, pp. 9-14
Du, B. ; Sonza Reorda, M. ; Sterpone, L. ; Parra, L. ; Portela-Garcia, M. ; Lindoso, A. ; Entrena, L. Exploiting the debug interface to support on-line test of control flow errors On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, pp. 98-103
Sonza Reorda, M. ; Sterpone, L. ; Ullah A. An error-detection and self-repairing method for dynamically and partially reconfigurable systems 18th IEEE European Test Symposium (ETS), 2013, pp. 1-7
Sterpone, L. ; Porrmann, M. ; Hagemeyer, J. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing IEEE Transactions on Computers, Volume: 62 , Issue: 8, pp. 1508 - 1525
Aloisio, A. ; Bocci, V. ; Giordano, R. ; Izzo, V. ; Sterpone, L. ; Violante, M. Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs IEEE Transactions on Nuclear Science, Volume: 60 , Issue: 5 , Part: 2, pp. 3502 - 3507
Sterpone, L. ; Sabena, D. ; Ullah, A. ; Porrmann, M. ; Hagemeyer, J. ; Ilstad, J. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 184-188
H. Hakobyan , P. Rech, M. Sonza Reorda, M. Violante Early Reliability Evaluation of a Biomedical System 2014 9th International Design & Test Symposium, Algiers, Algeria, December 2014. pp. 45-50
Sabena D., Sonza Reorda M., Sterpone L., Rech P., Carro L. Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results MICROELECTRONICS RELIABILITY, vol. 54 n. 11, pp. 2621-2628. - ISSN 0026-2714
De Carvalho M., Sabena D., Sonza Reorda M., Sterpone L., Rech P., Carro L. Fault Injection in GPGPU Cores to Validate and Debug Robust Parallel Applications IEEE 20th International On-Line Testing Symposium (IOLTS), Platja d'Aro, July 7 - 9, 2014. pp. 210-211
L. Bautista Gomez; F. Cappello; L. Carro; N. Debardeleben; B. Fang; S. Gurumurthi; K. Pattabiraman; P. Rech; M. Sonza Reorda GPGPUs: How to combine high computational power with high reliability Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, Dresden, Germany, March 2014
Sabena D., Sonza Reorda M., Sterpone L. On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 22 n. 4, pp. 813-823. - ISSN 1063-8210
Sabena D., Sonza Reorda M., Sterpone L. Soft Error Effects Analysis and Mitigation in VLIW Safety-Critical Applications IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, Mexico, October 6-8, 2014. pp. 135-140
Pilla L.L. ; Rech P. ; Silvestri F. ; Frost C. ; Navaux P.O.A. ; Sonza M. ; Carro L. Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 61 n. 4/1, pp. 1874-1880. - ISSN 0018-9499
L. Sterpone, B. Du Analysis and mitigation of single event effects on flash-based FPGAS IEEE 19th EUROPEAN TEST SYMPOSIUM (ETS), Paderborn, Germany. pp. 1-6
Cinzia Bernardeschi , Luca Cassano , Andrea Domenici , Luca Sterpone ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-based FPGAs IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 33 n. 9, pp. 1342-1355. - ISSN 0278-0070
Sanchez Ernesto , Sterpone Luca , Ullah Anees Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs 24th International Conference on Field Programmable Logic and Applications (FPL), 2014. pp. 1-6
Sabena D., Sterpone L., Schölzel M., Koal T., Vierhaus H.T., Wong S., Glein R., Rittner F., Stender C., Porrmann M., Hagemeyer J. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications 19th IEEE European Test Symposium (ETS), Paderborn, 26 May - 30 May 2014. pp. 175-182
Ullah Anees, Sterpone Luca Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs JOURNAL OF ELECTRONIC TESTING, vol. 30, pp. 425-442. - ISSN 0923-8174
Marco Desogus, Luca Sterpone, David Merodio Codinachs Validation of a tool for estimating the effects of Soft- Errors on modern SRAM-based FPGAs IEEE 20th International On-Line Testing Symposium, Platja d'Aro, Catalunya, Spain, 7 - 9 July 2014. pp. 111-115
A.A.C. Brandon, J.J. Hoozemans, J. Van Straten, A. F Lorenzon, A. L. Sartor, A.C.S. Beck, S. Wong A Sparse VLIW Instruction Encoding Scheme Compatible with Generic Binaries 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015), 7-9 December 2015, Mayan Riviera, Mexico
J.J. Hoozemans, J. Johansen, J. Van Straten, A.A.C. Brandon, S. Wong Multiple Contexts in a Multi-ported VLIW Register File Implementation 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015), 7-9 December 2015, Mayan Riviera, Mexico
J.J. Hoozemans, S. Wong, Z. Al-Ars Using VLIW Softcore Processors for Image Processing Applications International Conference On Embedded Computer Systems: Architectures, Modeling, And Simulation (SAMOS XV (2015)), 20-23 July 2015, Samos, Greece
A. L. Sartor, A. F Lorenzon, L. Carro, F. Kastensmidt, S. Wong, A.C.S. Beck A Novel Phase-based Low Overhead Fault Tolerance Approach for VLIW Processors IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 08-10 July 2015, Montpellier, France
J. Perez Acle, R. Cantoro, Hailemichael, T. Abel, E. Sanchez, M. Sonza Reorda Observability solutions for in-field functional test of processor-based systems XXX Conference on Design of Circuits and Integrated Systems (DCIS), Estoril (PT), November 25-27, 2015. pp. 1-6
E. Sanchez, M. Sonza Reorda On the Functional Test of Branch Prediction Units IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210
Matteo Sonza Reorda In-field test of safety-critical systems: is functional test a feasible solution? 2015 16th IEEE Latin-American Test Symposium (LATS)
A. Riefert, R. Cantoro, M. Sauer, M. Sonza Reorda, B. Becker On the Automatic Generation of SBST Test Programs for In-Field Test 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 9-13 March, 2015. pp. 1186-1191
W.H. Robinson, P. Rech, M. Aguirre, Barnard, A. Desogus, M. Entrena, L. Garcia-Valderas, M. Guertin, S.M. D. Kaeli, F.L. Kastensmidt, B.T. Kiddie, A. Sanchez-Clemente, M.S. Reorda, L. Sterpone, M. Wirthlin Using Benchmarks for Radiation Testing of Microprocessors and FPGAs IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 62 n. 6, pp. 2547-2554. - ISSN 0018-9499
Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich High Quality System Level Test and Diagnosis 2014 IEEE 23rd Asian Test Symposium, Hangzhou, China, November 2014. pp. 298-305