Fault-Tolerant System Design and Verification for Safety-Critical Applications

TOSCA

Project of the ALFA Programme



Project Description

The increasing popularity of computer-based systems in safety-critical applications in the information society pushed industry to need hardware designers and software engineers with new knowledge and skills, which enable them to able to face the problems posed by the implementation and verification of these systems. This demand occurs in the context of accelerated change, booming markets and shrinking time-to-market requirements. Furthermore, industries demand new techniques for introducing suitable mechanisms for guaranteeing the fault tolerance in the systems they produce, and for verifying their correct design and implementation. Although fault tolerant design is a rather old research and application area, its application to low-cost and high-volume products (e.g., in the automotive, biomedical, or telecommunication areas) makes most of the existing techniques simply not applicable, due to their high cost and long time for design and verification. The mobility supported by the network aims at providing the network institutions with the resources to train and update their young engineers and researchers in this area. 
 

Project Partners:
Politecnico di Torino, Dipartimento di Automatica e Informatica, Electronic CAD & Reliability Group (Project Coordinator) 
Instituto Superior Técnico (IST), Instituto de Engenharia de Sistemas e Computadores (INESC)
Institut National Polytechnique de Grenoble (INPG), Laboratoire TIMA
Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Departamento de Engenharia Elétrica 
Universidad de la República, Facultad de Ingeniería, Instituto de Ingeniería Eléctrica (IIE)
Universidad Nacional De La Plata, Facultad de Ingenieria, Laboratorio de Electronica Industrial, Control e Instrumentacion (LEICI) 

Beginning of the Activity

  • February 1st, 2002
Duration
  • 48 months
Meetings Workshops Seminars Documents Published Papers Tasks
  • VHDL Analysis and Manipulation for Fault Tolerance 
  • Fault Tolerance Validation through Fault Injection 
  • Fault Tolerance Validation through Irradiation 
  • Fault Modeling on VHDL descriptions 
Related Pages


 

Project Objectives
The rapidly increasing adoption of electronic systems for safety-critical applications even in low-cost and high-volume products demands for a new class of researchers and highly-skilled designers. The project aims at supporting the researcher mobility among a net of European and Latin-American Universities with well-recognized skills in this domain, and to increase the mobility of young researchers among the participating institutions. Thanks to the complementary experience of the network members, and to the novelty of problems and proposed solutions, the training activities will boost the diffusion of fault-tolerant design techniques in the interested countries, and will reinforce technology-transfer to industry. 

Contract number: AML/B7-311-97/0666/II-0086-FI

Last modified on November 4, 2005 by Maurizio Rebaudengo