Description

The purpose of this research project is to identify a way to use SRAM-based FPGAs in critical applications to substitute antifuse or Flash-based FPGAs, thus allowing on the one hand a substantial cost reduction and on the other a significant increase in the functionalities offered to critical application designers. The method to be developed will work with SRAM-based FPGAs currently on the market, and with possible new products that will be released in the future. It will not be based on modifications of the FPGA, and in particular of the configuration memory. Therefore the proposed method must be implemented at an abstraction level above the production technology of the SRAM-based FPGA.

In this project we are going to develop a procedure that will work on the functionality that the end user wants to implement on SRAM-based FPGAs. This means that the new methodology will be applied to the circuit (described at behavioral or structural level) that the critical application designer wants to implement with a SRAM-based FPGA.

The technique which is going to be developed will provide a solution which makes the circuits implemented on SRAM-based FPGAs insensitive to the modifications induced by ionizing radiation in the form of configuration memory SEUs.

From an experimental point of view, the project aims to validate the results obtained at the design level with measurements both with ion and neutron beams. The reasons behind the use of two radiation sources are several and complementary: on the one hand, experiments made with single-species and single-energy ion beams are easy to handle in Italy and yield SEU results simpler to interpret.

 

Research units

Università degli Studi di Padova - Dipartimento di Ingegneria dell'Informazione

Università degli Studi di Roma "Tor Vergata" - Dipartimento di Ingegneria Elettronica

Politecnico di Torino - Dipartimento di Automatica e Informatica

 

Papers published

A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
L. Sterpone, M. Violante
[accepted for publication on] IEEE Transactions on Nuclear Science, 2007

A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost
LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007

A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
[accepted for publication on] IEEE Transactions on Nuclear Science, 2007

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
[accepted for publication on] IOLTS2007: IEEE International On-Line Testing Symposium, 2007