Our group explores the adoption of Genetic Algorithms, and Evolutionary Computation techniques in general, for the solution of problems arising in Computer-Aided Design for VLSI circuit.

Evolutionary techniques are adopted to improve the design of digital hardware, either in an off-line fashion or an on-line one. In off-line optimization, we run the algorithm in software, and its results are then transferred to hardware. Examples of this approach are the optimization of the floorplan during silicon layout, the generation of test patterns aiming at maximizing the fault coverage in the final production testing of the circuit, and the partitioning and resynthesis of the circuit to decrease its power consumption.

On the other hand, on-line approaches transfer to the hardware itself all or part of the evolution and optimization processes. A series of successful experiments explores the adoption of Cellular Automata to generate test patterns: the CA evolves on its own, and with the feedback from the circuit aims at generating high-quality test patterns. The circuit, coupled with the CA, is therefore able to evolve on its own suitable test sequences, completely in hardware. This system also includes a software component, that is used to choose the best configuration for the CA in order to improve its learning capability.

Research is also carried on to develop evolutionary algorithms that are easier to implement in hardware, e.g., that don't require explicit models of the population, or ranking of individuals.


Uses of evolvable hardware in:

Contact information

Giovanni Squillero
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
I-10129 Torino
Tel: +39-011564.7186
Fax: +39-011564.7099
E-mail: giovanni . squilleroat
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