The task of a test pattern generation algorithm is to produce a sequence of inputs able to excite and propagate a target fault towards the circuit outputs. A pattern generated in this way by a classical ATPG usually produces a high circuit switching activity, which is the major cause of heat dissipation in a CMOS circuit. Both average and peak switching activity can produce critical side effects on the circuit under test:
- high average switching activity corresponds to an average power consumption able to reduce the circuit reliability: high power consumption corresponds to higher temperatures, which is one of the major factors that determine electro-migration rate;
- switching activity much higher than that during circuit normal operation can cause a peak power consumption higher than a given threshold that can permanently damage the circuit under test.
When dealing with high performance power hungry chips, heat dissipation during test application becomes thus a problem that requires close attention.
As a first step towards a low power test generation tool, we have proposed a methodology to reduce the energy consumed during test by optimally selecting the test sequences coming from a conventional ATPG when a given degree of redundancy is provided.
Current work is on the reduction of peak power consumption by exploiting symbolic methods to modify the test pattern produced by a conventional ATPG with a negligible impact on the attained fault coverage.Low Power Test.
- Matteo Sonza Reorda
- Fulvio Corno
- Maurizio Rebaudengo
- Massimo Violante
|Matteo Sonza Reorda|
|Politecnico di Torino|
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
|E-mail: matteo . sonzareorda|
Personal web page: http://www.cad.polito.it/staff/sonza/
Politecnico info page: http://www.dauin.polito.it/en/personale/scheda/(matricola)/001894
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